"Area and Speed Efficient Implementation of Symmetric FIR Digital Filter through Reduced Parallel LUT Decomposed DA Approach"
S. C. Prasanna1,
S. P. Joy Vasantha Rani2
published by Circuits and Systems, Vol.7 No.8, 2016
has been cited by the following article(s):
Decimator Systolic Arrays Design Space Exploration for Multirate Signal Processing Applications