"Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits"
Almotasem Bellah Alajlouni,
published by Circuits and Systems, Vol.4 No.2, 2013
has been cited by the following article(s):
Research of timing graph traversal algorithm in static timing analysis based on FPGA
Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing