Through the last decade, the progress of power electronics along with the regular cost reduction, reliability, power capability and high efficiency, has made it the most alerting for researchers’ attention . This progress has made the ability to develop voltage source inverters (VSI) which can control voltage and frequency simultaneously, therefore they are considered the best solution for many applications. The conventional three-level H-bridge inverter circuit is the first generation of inverter topologies  . As many applications require high efficiency with fewer harmonic contents, a demand for the higher voltage rating multilevel inverter (MLI) has evolved.
One of the leading advances for MLIs is the improvement in power electronics which have been used to fulfill the requirements for many applications for low/medium voltage electrical utility . MLI is a good solution for improving the performance of many industrial applications such as renewable energy systems  , motor drives  , uninterruptable power supplies (UPS), flexible AC transmission systems (FACTS)  , etc. Another advantage of MLI is discarding the need for a step-up transformer which is needed in high voltage applications that reduces the overall cost and size of the inverter circuits .
A high number of the stepped output voltage from MLI leads to the output voltage shape to be close to a sinusoidal waveform. This leads to the high quality in output voltage with good total harmonic distortion (THD), low dv/dt stress in addition to the reduction in output filter size . They are promising as they become more attractive due to their inherent merits as it becomes cheaper, lighter, and compact. Mainly, popular topologies of MLIs are categorized into 1) diode-clamped MLI (DCMLI) which was proposed by Nabae et al.  , 2) flying capacitor MLI (FCMLI) which was introduced by Meynard and Foch  and 3) cascaded H-bridge MLI (CHBMLI)  .
DCMLI has two advantages over conventional H-bridge inverter; the higher voltage capability and a reduced harmonic content. However, it suffers from the unbalance of voltage in the DC-link capacitors, on the other hand, it requires a large number of clamping diodes, which increases the complexity with higher voltage levels  . FCMLI has lesser number of required DC voltage sources  however, it has two main problems; it requires a large number of capacitors in addition to the difficulty to achieve the capacitor voltage balance  . In order to overcome the limitations of DCMLI and FCMLI, CHBMLI has been presented.
CHBMLI consists of several H-bridge inverters with separate DC voltage sources. It has two structures, namely the symmetric and the asymmetric CHBMLI  . In symmetric CHBMLI, all the separated DC voltage sources have the same magnitudes. However, it utilizes a large number of power switches in addition to gate drive circuits to obtain a large number of levels, which increases the cost of the overall circuit. A lesser number of power switches had been used in the asymmetric structure, on the other hand, it suffers from voltage stress in most of the power switches and voltage sources . The main challenging issue is to obtain a high number of levels with lesser voltage stress, fewer power switches in addition to lesser DC voltage sources. Recently, many topologies have been recommended as a replacement for CHBMLI.
In order to generate more number of levels, many researchers have presented many developed topologies. Each one of these topologies has merits and demerits due to the number of used components such as power switches and DC voltage sources, power losses and voltage stress on the switches. Using a large number of power switches, gate drive circuits in  leads to increased circuit size and manufacturing costs. By using the bidirectional switches to obtain more number of levels, the number of power switches and drive circuits in  is reduced. However, a large number of components conduct in each mode which may lead to high power loss. In  a single phase seven-level inverter has been proposed by using only seven power switches in addition to two power diode. However, this topology uses a large number of components.
The modular multilevel inverter (MMLI) has been proposed in . To generate higher levels by this topology, three components (one DC source and two power switches) are added which increases the number of components. In order to overcome the aforementioned issues, a new multilevel inverter has been presented in this paper. The proposed topology has an optimum number of power components and hence fewer gate drive circuits in addition to less circuit layout complexity for a high number of levels compared with other topologies mentioned in    .
2. Proposed Single-Phase Multilevel Inverter
Figure 1 shows a modified structure for the proposed single-phase MLI which reduces the overall circuit by one power switch compared with the proposed circuits in  . The proposed MLI comprises of “n” segments each segment is composed of a DC voltage source in series with one power switch without fast recovery diode. Only the first segment has one DC voltage source, with value of , and one power switch, , with a fast recovery diode where diode is used to generate the first level, in contrast, the power switch is used to provide a freewheeling path for inductive loads.
Figure 1. Proposed modular multilevel inverter.
For the proposed MLI, the relation between the number of symmetric DC voltage sources, , and the number of power switches, based on the maximum number of levels, , and are calculated as follows:
The device rating of the power switch in any topology must be selected carefully. This is because most of the power switches may block different voltage. Maximum blocked voltage is the most important parameter and must be taken into account in construction of any MLI topology as the cost of MLI based on this value. MBV is calculated by summing the blocked voltage across each power switches. The blocked voltage of power switches in level and generation parts in addition, MBV values are calculated as follow:
DC voltage sources in level generation part can be replaced with series-connected capacitors supplied from single DC voltage source where the DC source can be adopted by some applications such as photovoltaic system. However, the voltage across the capacitors will deviate during the switching process at generating levels. Therefore, it is necessary to balance the voltage across the capacitors.
To strengthen the powerful merit of the proposed topology, several comparisons have been presented to verify the merits and demerits of the proposed MMLI. Several topologies of MMLI have been presented in the past few years which have the ability to provide symmetrical and asymmetrical operation. To make the comparisons fair and rational, all topologies used in the comparisons are used in its symmetrical operation. The proposed inverter for simplicity in comparisons is mentioned as “P”. CHB-MLI is presented in . This topology is considered for comparisons by “ ”. Another topology is presented in  which offers symmetry and asymmetry from its structure is described in “ ”. “ ” describe an MLI presented in  based on switched DC sources which can offer asymmetry operation. Several topologies are presented in      which offer modularity with low number of components are described by “ ”-“ ”. A high number of components topology is presented in  which is described by “ ”.
The main aim of introducing new topology is the increment in number of levels using lower number of components. As the number of components increased, the switching losses, size, and cost will increase. The comparisons between different topologies must be made in the requirements of switching devices to present switching losses and in the total number of components to present overall cost of the presented topology for a given number of levels. In addition, the maximum blocked voltage by the power switches must be taken into account as it provides the overall cost of the presented topology. Figure 2(a) presents the comparison between the proposed topology “P” and most recent topologies. As shown, the proposed inverter presents lower number of components for introducing higher number of levels. Another important term in introducing any topology is the number of conducting devices for generating given number of levels. Level to conducting devices ratio (LCD) means the number of conducing devices including power switches and diodes are included for a given number of levels. This ratio provides amount of losses based on number of conducting devices. High LCD ratio means low number of conducting devices along with low switching losses and high efficiency the topology will offer at higher number of levels. Figure 2(b) displays LCD ratio comparison with different topologies. As seen, the proposed inverter offers better values of LCD ratio compared with other presented topologies as only three devices conduct at any level. While, as shown in Figure 2(c), “ ” and “ ” offer lower value of blocked voltage compared with the proposed topology and “ ”. However, the proposed topology still offers better value compared with other topologies.
Figure 2. Comparison between the proposed topology with other topologies.
3. Single-Phase Seven-Level Inverter
The structure of the proposed single-phase seven-level PWM inverter is indicated in Figure 1. This topology comprises three symmetrical DC voltage sources and seven power switches. The inverter output voltage will have seven state i.e. . It consists of two parts; the polarity generation part which is a conventional H-bridge inverter and the level generation part. As shown in this figure the switches , , , and should be power switches with an antiparallel diode to provide the path for load current, however, power switches and should be without anti-parallel diode to avoid the short circuit problem between DC voltage sources. As the power switches are not ideal so dead-time has been taken into account. The main function of the polarity generation part is to obtain the zero state on the AC load voltage while, the main purpose of the level generation part is to obtain different output voltage levels.
3.2. Generation of Levels
In order to achieve a balanced output voltage levels, the DC voltage sources in each segment must be symmetrical ( ). As the load is bi-directional, the output voltage from the proposed inverter has ten states as illustrated in Table 1. The output voltage levels according to the ON state condition are indicated in Figure 3.
4. Switching Algorithm
The switching pattern for the proposed seven-level PWM inverter is generated by comparing a rectified sinusoidal reference signal (i.e. ) with three in-phase triangle carrier signals (i.e. , , and ) having same switching frequency, same peak value but different in offset voltage which is the level shifted PWM (LSPWM) methodology as shown in Figure 4. The intersection between and occurs with a modulation index (MI), as calculated
Table 1. Switching states.
Figure 3. Generation of output voltage levels.
Figure 4. Switching pattern of single-phase seven-level inverter.
by Equation (6), between 0 and 0.33 and the output voltage will have three levels i.e. 0). However, if the intersection occurs between and , MI will be in the range of 0.33 and 0.67 and the output voltage will have five levels (i.e. , , 0). By contrast, if the intersection occurs between and , MI will be greater than 0.67 and the output voltage will have seven levels (i.e. , , , 0).
5. Voltage Control Strategy
The closed loop voltage regulation of the proposed seven-level inverter is shown in Figure 5. In order to reduce the ripple contents in output voltage and current of the load, an LC filter has been used. A PI controller is used to regulate the output voltage at the load terminals to be near sinusoidal similar to the reference voltage . The actual voltage is compared with the reference one to obtain an error signal which applied to a PI controller to provide the modulated signal (U). After that, the modulated signal is compared with the LSPWM carriers to provide the switching states.
6. Experimental Validation
The overall experimental prototype has been implemented and tested to prove the validity of the proposed inverter. Figure 6 presents the experimental prototype of the proposed seven-level inverter. The experimental results for all variables are taken by a digital oscilloscope (Tektronix MSO2014). The output load current ( ) is measured using a current probe (Tektronix TCP 300). The dSPACE_CP 1103 is chosen as the controller for the proposed inverter and experimental results’ efficiency is taken by power analyzer (Yokogawa WT1800). THD analysis of the terminal and load voltages ( , ) at different values of MI are also calculated. The single-phase seven-level inverter is implemented using the five power switches ( , , , and ) with MOSFET (IRFP460) in contrast, the two power switches ( and ) as IGBT/without anti-parallel diode (IGW50N65F5FKSA1).
A single-phase seven-level inverter to feed a stand-alone resistive load in addition to an LC filter has been evaluated. Experimental results have been investigated at 10 kHz as a switching frequency ( ) with three identical DC voltage sources of 50 V. The experimental parameters are given in Table 2. Dead time is taken into account with 2 µs. As mentioned before, the number of output levels depends mainly on MI; different values of MI are investigated to prove the validity of the proposed inverter.
Table 2. Experimental system parameters.
Figure 5. Control scheme.
Figure 6. Experimental prototype. 1) PC; 2) dSPACE_CP1103; 3) Gate drive circuit; 4) Proposed MLI; 5) Voltage sensor circuit; 6) DC voltage sources; 7) Current probe; 8) Power analyzer WT1800; 9) Oscilloscope Tektronix; 10) Inductive filter; 11) Capacitive filter; 12) Resistive load; 13) Inductive load.
Figure 7 shows the experimental results of the inverter output voltage ( ), reference and load voltage ( , ) and load current ( ) at different values of MI. The proposed inverter output can be three, five, and seven levels. Figure 7(a) provides the inverter three-level voltage, reference, output voltage, and output current for MI = 0.3 and the peak value of 45 V of reference voltage. As can be seen the actual load voltage follows the reference voltage. The THD has been reached (up to 600 kHz) from 58.27% for inverter output voltage to 5.02% for the load output voltage. For MI = 0.6, the inverter provides five levels at its output for a peak value of 90 V as shown in Figure 7(b) with THD of 31.46% and 2.42% for the inverter and load output voltage, respectively. The seven-level result is shown in Figure 7(c) by taking reference voltage as 135 V as a peak value at MI = 0.9. 21.82% and 2.13% are the THD values for the inverter and load output voltage, respectively. From Figures 7(a)-(c), it is clear that the load output voltage ( ) tracks the reference voltage ( ).
Figure 7. Experimental results for single-phase seven-level inverter with resistive load. (a) MI = 0.3; (b) MI = 0.6; (c) MI = 0.9.
In order to ensure the stability of the proposed inverter, a step change in the inverter output voltage according to change in the modulation index has been made. Figure 8 provides a change in MI from 0.3 to 0.9 thus the number of the output voltage changes from three-level to seven-level with resistive load of 42 Ω. As shown, the output voltage provides fast response to the step change. Figures 9(a)-(c) present the RMS value of output voltage and current, and the output power and inverter efficiency for MI = 0.3, 0.6, and 0.9, respectively.
Figure 8. Experimental results for single-phase seven-level inverter with step change in MI.
Figure 9. Experimental results for output power and efficency. (a) MI = 0.3; (b) MI = 0.6; (c) MI = 0.9.
Also, the proposed inverter has been operated when the load is R-L load of (Rl = 72 Ω and Ll = 160 mH). The experimental results with R-L load are shown in Figure 10. Seven-level output voltage at MI = 0.9 with inductive load is shown in Figure 10(a) while, a step change has been made with inductive load as shown in Figure 10(b). As seen that the proposed inverter can be operated under variation in MI and type of load. Figure 11 presents the efficiency with different values of output power.
A comparison has been made with recent topologies in the value of the efficiency and THD of the proposed inverter as presented in Table 3. From Table 3, THD of the proposed inverter is better than in  for seven-level output voltage due to the switching pattern used in the mentioned reference has distorted the output voltage also efficiency is better due to lower switching devices used in the proposed inverter. Also, five-level output voltage in  almost has better efficiency compared with the proposed inverter with five levels due to the inverter is operated at higher rated power compared with the proposed inverter. As shown from the figure the inverter efficiency is increased and THD is reduced with an increment of MI.
In this paper, a new multilevel inverter topology was proposed which can be extended to any number of levels by adding one DC source and one power switch for the repeating stages. A comparative study presented the merits of the proposed inverter which offers lower circuit components, total blocked voltage, and level to switching device ratio compared with most recent topologies, thereby reducing circuit complexity and total cost. Experimental results have been carried out to provide the validity of the proposed topology for a voltage closed-loop operation under variation on types of load and modulation index. The experimental results provide low THD value of 2.13% for the load output
Figure 10. Experimental results with inductive load. (a) MI = 0.9; (b) Step change in MI.
Figure 11. Efficiency versus output power.
Table 3. Comparison in THD and efficiency.
voltage and efficiency of 92%. The low THD value and high efficiency present the strength of the proposed inverter.
The authors would like to thank General Administration of Postgraduate Studies and Researches-Scientific Research Administration-South Valley University for financial support of this work.
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