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 JCC  Vol.6 No.10 , October 2018
An Efficient Overflow Detection and Correction Scheme in RNS Addition through Magnitude Evaluation
Abstract: Number Systems are media for representing numbers; the popular ones being the Weighted Number Systems (WNS), which sometimes propagate carries during arithmetic computations. The other category, Un-Weighted Number Systems, of which the Residue Number System (RNS) belongs, do not carry weights but have not yet found widespread usage in general purpose computing as a result of some challenges; one of the main challenges of RNS is overflow detection and correction. The presence of errors in calculated values due to such factors as overflow means that systems built on this number system will continue to fail until serious steps are taken to resolve the issue. In this paper, a scheme for detecting and correcting overflow during RNS addition is presented. The proposed scheme used mixed radix digits to evaluate the magnitude of the addends in order to detect the occurrence of overflow in their sum. The scheme also demonstrated a simplified technique of correcting the overflow in the event that it occurs. An analysis of the hardware requirements and speed limitations of the scheme showed that it performs considerably better in relation to similar state of art schemes.

1. Introduction

The Residue Number System (RNS) has gained prominence in recent years due to its seemingly inherent features such as parallelism and carry-propagation free arithmetic computations. Notwithstanding the fact that, RNS is currently being applied in Digital Signal Processing (DSP) intensive computations like digital filtering, convolutions, correlations, Discrete Fourier Transform (DFT) computations, Fast Fourier Transform (FFT) computations and Direct Digital Frequency synthesis [1] [2] [3] ; researchers in the area are still working hard around the clock in order that the RNS becomes a general purpose processor. These efforts have not completely come to fruition because of challenges, including conversion to and from RNS and decimal/binary number systems, the moduli sets to use, overflow detection and correction, magnitude evaluation, and scaling.

An RNS number X, is represented as x i = | X | m i , where m i = { m 1 , m 2 , , m n } , a set of pairwise relatively prime integers such that m 1 m 2 m n and gcd ( m 1 , m 2 ) , , gcd ( m n 1 , m 1 ) = 1 . The residue set x i = [ x 1 , x 2 , , x n ] is uniquely represented provided X lies within the legitimate range [ 0 , M 1 ] where M = i = 1 n m i is the Dynamic Range (DR) for the chosen moduli set. Let X and Y be two different integers within the DR, if X Y , ( are the arithmetic operations + , , × , ÷ ), results in a value that is outside the legitimate range, then overflow is said to have occurred.

Overflow in general computing occurs if a calculated value is greater than its intended storage location in memory [4] [5] ; this relates to the DR in RNS which situation usually arises during addition and multiplication operations and failure to detect it will lead to improper or wrong representation of numbers and calculated results. Thus detecting overflow is one of the fundamental issues in the design of efficient RNS systems [6] .

The conversion of an RNS number into its decimal/binary equivalent number (a process called reverse conversion) has long been mainly based on the Chinese Remainder Theorem (CRT) and the Mixed Radix Conversion (MRC) techniques with few modifications being their variants of recent times. Whiles the former deals with the modulo-M operation, the later does not but computes sequentially which tends to reduce the complexity of the architecture. Computations can be done using the MRC as follows:

X = e 1 + e 2 m 1 + e 3 m 1 m 2 + + e n m 1 m 2 m n 1 (1)

where e i , i = 1 , 2 , , n are the Mixed Radix Digits (MRDs) and computed as follows:

e 1 = x 1

e 2 = | ( x 2 e 1 ) | m 1 1 | m 2 | m 2

e 3 = | ( ( x 3 e 1 ) | m 1 1 | m 3 e 2 ) | m 2 1 | m 3 | m 3

e n = | ( ( ( x 3 e 1 ) | m 1 1 | m n e 2 ) | m 2 1 | m n e n 1 ) | m n 1 1 | m n | m n (2)

The MRDs e i are within the range 0 e i m i , and a positive number, X, in the interval [ 0 , M ] can be uniquely represented. The magnitude of a number can become crucial in the determination overflow in RNS. The sign of an RNS number is determined by partitioning M into two parts: 0 X < M / 2 (for positive integers) and M / 2 X < M (for negative integers).

Recently, some techniques have been developed to detect overflow without necessarily completing the reverse conversion process; in [7] , an algorithm to detect overflow in the moduli set ( 2 n 3 , 2 n 1 , 2 n , 2 n + 1 , 2 n + 3 ) by adding a redundant modulus 2 to this moduli set and making use of ROM and XOR gates was proposed. In [8] , a method for detecting overflow in the moduli set ( 2 n 1 , 2 n , 2 n + 1 ) based on group of numbers is presented where numbers within [ 0 , M 1 ] are distributed among several groups. Then, by using the groupings, the scheme is able to diagnose in the process of addition of two numbers, whether overflow has occurred or not. The scheme in [3] evaluated the sign of the sum of two numbers X and Y and used it to detect overflow but adopted a residue-to-binary converter proposed by [9] . The scheme in [10] presented a scheme by an Operands Examination Method for overflow detection for the moduli set ( 2 n 1 , 2 n , 2 n + 1 ) during RNS addition. All these schemes either relied on complete reverse conversion process as in the case of [3] , or other costly and time consuming procedures such as base extension, group number and sign detection as in [8] and [10] .

In this paper, a new technique for detecting and correcting overflow during the addition of two RNS numbers for the moduli set { 2 n 1 , 2 n , 2 n + 1 } is presented; the technique evaluates the sign of an RNS number by performing a partial reverse conversion using the mixed radix conversion method. The sign of the addends is evaluated using only the MRDs, which is then used to detect the occurrence of overflow during RNS addition. The rest of the paper is organized as follows: Section 2 presents the proposed method, an anticipated hardware implementation (albeit theoretical) is presented in Section 3 with its realization in Section 4. Numerical illustrations are shown in Section 5 whiles the performance of the proposed scheme is evaluated in Section 6. The final part of this paper is the conclusion in Section 7.

2. Proposed Method

Given the moduli set { 2 n 1 , 2 n , 2 n + 1 } , where m 1 = 2 n + 1 , m 2 = 2 n and m 3 = 2 n 1 , then

M = 2 n ( 2 n + 1 ) ( 2 n 1 ) (3)

This implies

M / 2 = 2 n 1 ( 2 n + 1 ) ( 2 n 1 ) = ( 2 n + 1 ) ( 2 2 n 1 2 n 1 ) (4)

Lemma 1: Given the moduli set { 2 n 1 , 2 n , 2 n + 1 } , where m 1 = 2 n + 1 , m 2 = 2 n and m 3 = 2 n 1 for every integer n > 1 , the following hold true [10] :

| m 1 1 | m 2 = 1 (5)

| m 2 1 | m 3 = 1 (6)

| m 1 1 | m 3 = 2 n 1 (7)

Therefore, we can re-write (2) as;

e 1 = x 1

e 2 = | ( x 2 e 1 ) 1 | 2 n = | x 2 x 1 | 2 n

e 3 = | ( ( x 3 e 1 ) 2 n 1 e 2 ) 1 | 2 n 1 = | ( x 3 e 1 ) 2 n 1 e 2 | 2 n 1 (8)

Theorem 1: For the given moduli set, any integer X M / 2 if and only if

e 3 = 2 n 2 n 1 (9)

or

e 3 = 2 n 2 n 1 1 AND e 2 = 2 n 2 n 1 (10)

for any n > 1 .

Proof: If it can be shown that by substituting (9) and (10) into Equation (4) that, X ( 2 n + 1 ) ( 2 2 n 1 2 n 1 ) then, it implies X M / 2 .

Assume (9) is true, then

X = e 1 + ( 2 n + 1 ) e 2 + ( 2 n 2 n 1 ) 2 n ( 2 n + 1 ) = e 1 + ( 2 n + 1 ) [ e 2 + 2 2 n 2 2 n 1 ] > ( 2 n + 1 ) ( 2 2 n 1 2 n 1 ) , n > 1

Also, assume (10) is true, then

X e 1 + ( 2 n 2 n 1 ) ( 2 n + 1 ) + ( 2 n 2 n 1 1 ) ( 2 2 n + 2 n ) = e 1 + ( 2 n + 1 ) [ 2 2 n 2 2 n 1 2 n 1 ] ( 2 n + 1 ) ( 2 2 n 1 2 n 1 ) , n > 1

Thus, from (9) and (10), it is possible to determine the sign of an RNS number X; whether X M / 2 (for a negative number) or X < M / 2 (for a positive number).

The proposed method uses comparison by computing the MRDs of each of the addends to determine which half of the RNS range it belongs rather than performing a full reverse conversion. To detect overflow during addition of two addends X and Y based on the moduli set { 2 n 1 , 2 n , 2 n + 1 } , a single bit that indicates the sign of that addend is defined. Now, based on this bit, three cases will then be considered:

1) Overflow will definitely occur if both of the addends are equal to or greater than half of the dynamic range (M/2).

2) Overflow will not occur if both of the addends are less than M/2.

3) Overflow may or may not occur if only one of the addends is equal or greater than M/2 and will require further processing to determine whether overflow will occur or not.

Let the magnitude evaluation of the addends ( X , Y ) be represented by β , such that if β = 1 or β = 0 represents a positive number or a negative number respectively as shown in Equation (11). The evaluation of the undetermined case in (3) is also represented by a single bit λ in (12).

β = { 1 ; e 3 = 2 n 2 n 1 1 ; e 3 = 2 n 2 n 1 1 AND e 2 = 2 n 2 n 1 0 ; otherwise (11)

and,

λ = { 1 ; x 1 + y 1 2 n + 1 0 ; otherwise (12)

The proposed method will then detect overflow as follows:

o v e r f l o w = { 0 ; β X + β Y = 0 1 ; β X β Y = 1 λ ; β X β Y = 1 (13)

where ( + , , ) refer to the logical operations (OR, AND, XOR), respectively. For clarity, “1” means overflow occurs whilst “0” means no overflow.

Correction Unit

Let Z be the sum of the two addends. By substituting the individual MRDs for both addends (X and Y), Z can be obtained as follows;

Z = X + Y = [ e 1 ( X ) + e 2 ( X ) m 1 + e 3 ( X ) m 1 m 2 ] + [ e 1 ( Y ) + e 2 ( Y ) m 1 + e 3 ( Y ) m 1 m 2 ] = ( e 1 ( X ) + e 1 ( Y ) ) + ( e 2 ( X ) + e 2 ( Y ) ) m 1 + ( e 3 ( X ) + e 3 ( Y ) ) m 1 m 2

by letting ψ i = e i ( X ) + e i ( Y ) , we shall have

Z = ψ 1 + ψ 2 m 1 + ψ m 1 m 2 (14)

Thus by adding the individual MRDs of the two addends, we obtain the sum Z according to (1) without having to compute separately for its MRDs. The value of Z obtained from (14) is the correct result of the addition whether overflow occurs or not. In case of overflow occurrence, the redundant modulus is employed by shifting M one bit to the left in order to accommodate the value.

3. Hardware Implementation

From Equation (8), the MRD’s e 1 , e 2 and e 3 can be represented in binary as;

e 1 = e 1 , n e 1 , n 1 e 1 , 1 e 1 , 0 n + 1 (15)

e 2 = e 2 , n 1 e 2 , n 2 e 2 , 1 e 2 , 0 n (16)

e 3 = e 3 , n 1 e 3 , n 2 e 3 , 1 e 3 , 0 n (17)

Equations (15) to (17) can further be simplified as follows;

e 1 = x 1 = x 1 , n x 1 , n 1 x 1 , 1 x 1 , 0 n + 1 (18)

e 2 = | x 2 x 1 | 2 n = | x 2 + t 1 | 2 n = | x 2 , n 1 x 2 , n 2 x 2 , 1 x 2 , 0 n + t 1 , n 1 t 1 , n 2 t 1 , 1 t 1 , 0 n | 2 n = e 2 , n 1 e 2 , n 2 e 2 , 1 e 2 , 0 n n (19)

where,

t 1 = | x 1 | 2 n = | ( x 1 , n x 1 , n 1 x 1 , 1 x 1 , 0 n + 1 ) | 2 n = | ( x 1 , n 1 x 1 , n 2 x 1 , 1 x 1 , 0 n ) | 2 n = | x ¯ 1 , n 1 x ¯ 1 , n 2 x ¯ 1 , 1 x ¯ 1 , 0 n | 2 n (20)

and

e 3 = | 2 n 1 x 3 2 n 1 e 1 e 2 | 2 n 1 = | t 2 + t 3 + t 4 | 2 n 1 = | t 2 , n 1 t 2 , 1 t 2 , 0 n + t 3 , n 1 t 3 , 1 t 3 , 0 n + t 4 , n 1 t 4 , 1 t 4 , 0 n | 2 n 1 = e 3 , n 1 e 3 , n 2 e 3 , 1 e 3 , 0 n (21)

where

t 2 = | 2 n 1 x 3 | 2 n 1 = | 2 n 1 ( x 3 , n 1 x 3 , n 2 x 3 , 1 x 3 , 0 ) n | 2 n 1 = x 3 , 0 x 3 , n 1 x 3 , 2 x 3 , 1 n (22)

t 3 = | 2 n 1 x 1 | 2 n 1 = | 2 n 1 ( x 1 , n x 1 , n 1 x 1 , 1 x 1 , 0 ) n + 1 | 2 n 1 = | 2 n 1 ( x 1 , n × 2 n + x 1 , n 1 x 1 , 1 x 1 , 0 n ) | 2 n 1 (23)

Since, x 1 is a number that is smaller than 2 n + 1 , two cases are considered for x 1 . First, when x 1 is smaller than 2 n , and second, when x 1 is equal to 2 n [11] . If x 1 , n = 0 , we have

t 31 = | 2 n 1 ( x 1 , n 1 x 1 , n 2 x 1 , 1 x 1 , 0 ) n | 2 n 1 = x ¯ 1 , 0 x ¯ 1 , n 1 x ¯ 1 , 2 x ¯ 1 , 1 n (24)

Else if x 1 , n = 1 , the following binary vector can be obtained as

t 32 = | 2 n 1 × 2 n ( 00 0 n 1 x 1 , n ) | 2 n 1 = 0 11 1 n 1 (25)

Therefore, t 3 is calculated as

t 3 = { t 31 , if x 1 , n = 0 t 32 , if x 1 , n = 1 (26)

And finally,

t 4 = | e 2 | 2 n 1 = | ( e 2 , n 1 e 2 , n 2 e 2 , 1 e 2 , 0 ) n | 2 n 1 = e ¯ 2 , n 1 e ¯ 2 , n 2 e ¯ 2 , 1 e ¯ 2 , 0 n (27)

Let γ and ω represent the MRDs of the two integers X and Y respectively. Thus from equations (19) to (21), we have

ψ i = γ i + ω i (28)

which implies

ψ 1 = γ 1 + ω 1 = γ 1 , n γ 1 , n 1 γ 1 , 0 n + 1 + ω 1 , n ω 1 , n 1 ω 1 , 0 n + 1 = ψ 1 , n ψ 1 , n 1 ψ 1 , 0 (29)

ψ 2 = γ 2 + ω 2 = γ 2 , n 1 γ 2 , n 2 γ 2 , 0 n + 1 + ω 2 , n 1 ω 2 , 0 n + 1 = ψ 2 , n 1 ψ 2 , n 2 ψ 2 , 0 (30)

finally,

ψ 3 = γ 3 + ω 3 = γ 3 , n 1 γ 3 , n 2 γ 3 , 0 n + 1 + ω 3 , n 1 ω 3 , 0 n + 1 = ψ 3 , n 1 ψ 3 , n 2 ψ 3 , 0 (31)

and so, Z is implemented as;

Z = z 1 + z 3 + z 4 = 0 0 2 n z 1 , n z 1 , 0 n + 1 + 0 z 3 , 3 n 1 z 3 , 0 3 n + 0 0 n + 1 z 4 , 2 n 1 z 4 , 0 2 n 3 n + 1 (32)

where,

z 1 = ψ 1 (33)

z 3 = z 2 + 2 2 n ψ 3 = ψ 3 , n 1 ψ 3 , 0 n 00 0 2 n z 2 , 2 n 1 z 2 , 0 2 n = z 3 , 3 n 1 z 3 , 3 n 2 z 3 , 1 z 3 , 0 (34)

z 2 = 2 n ψ 2 + ψ 2 = ψ 2 , n 1 ψ 2 , 0 n 00 0 n ψ 2 , n 1 ψ 2 , 0 n = z 2 , 2 n 1 z 2 , 2 n 2 z 2 , 1 z 2 , 0 (35)

and,

z 4 = 2 n ψ 3 = ψ 3 , n 1 ψ 3 , 1 ψ 3 , 0 n 00 0 n = z 4 , 2 n 1 z 4 , 2 n 2 z 4 , 1 z 4 , 0 (36)

4. Hardware Realization

The hardware realization of the proposed scheme is divided into four parts as shown in Figures 1-4. First is the Partial Conversion Part (PCP) shown in Figure 1, which evaluates the MRDs based on (18), (19) and (21) with their parameters clearly defined according to (20) and (21) - (27). The PCP begins with an Operands Preparation Unit (OPU) which prepares the operands in (20), (22) and (26) by simply manipulating the routing of the bits of the residues. Also, an n-bit 2:1 Multiplexer (MUX) is used for obtaining (26). ADD1 is an n-bit Carry Propagate Adder (CPA) and is used to compute (19), meanwhile (21) is obtained by using an ( n 1 ) -bit CPA as ADD2 whose save ( s 1 ) and carry ( c 1 ) are then added using ADD3 which is also an ( n 1 ) -bit CPA. These MRDs are used to determine the sign of the RNS number in Figure 2. Thus, the critical path for the PCP unit is made up of one ( 2 n ) modulo adder and two ( 2 n 1 ) modulo adders.

Figure 1. Partial conversion part (PCP).

Figure 2. Magnitude evaluation part (MEP).

Figure 3. Overflow detection part (ODP).

Figure 4. Overflow correction part (OCP).

Second, is the Magnitude Evaluation Part (MEP) shown in Figure 2, which evaluates whether an RNS number is positive or negative according to Equation (11). The MEP uses one AND gate and an OR gate. These are both two input monotonic gates. Next, is the Overflow Detection Part (ODP) which compares the sign bits of the two addends by using an AND gate according to (13) which is then ORed with the evaluated bit of the undetermined case in (12) as shown in Figure 3. This is where the scheme detects the occurrence of overflow during the addition of two numbers.

Lastly, in Figure 4 is the Overflow Correction Part (OCP). The OCP evaluates the individual MRDs of the two addends separately to achieve the sum Z in (14). This is done using five adders; four regular CPAs and one carry save adder (CSA). This is computed according to (29) - (36). ADD4, ADD5 and ADD6 add separately the MRDs e 1 , e 2 and e 3 respectively for the two addends. The result of ADD4 is of importance because it is used in evaluating the undetermined case in (12). z 2 is a result of concatenation as well as z 3 which do not require any hardware. ADD7 is a CSA which computes the result of z 1 , z 2 and z 3 whose save ( s 2 ) and carry ( c 2 ) are added using ADD 8 which is a CPA in order to get accurate sum Z whether overflow occurs or not. The schematic diagrams for the proposed scheme are presented in Figures 1-4.

The area (A) and time (D) requirements of the proposed scheme are estimated based on the unit-gate model as used in [12] and [13] for fair comparison. In this model, each two-input monotonic gate such as AND, OR, NAND, NOR has area A = 1 and delay D = 1 , each two-input gate XOR/XNOR has A = D = 2 , The area and delay of an inverter is a negligible fraction of a unit, and it is thus assumed to require zero units of area and delay [14] . A 2:1 multiplexer has an area A = 3 and delay D = 2 ; A full adder has an area of seven gates and a delay of four gates but a CSA has a constant delay. Also, the adder requirements based on this model as presented in [14] is adopted for the comparison since the adopted adders are similar to the adders used for the proposed scheme. The results state that an estimation modulo;

( 2 n ) : A = 5 n + ( 3 2 ) n log 2 n ,

D = 2 log 2 n + 3

( 2 n 1 ) : A = 12 n + 3 n ( log 2 n 1 ) ,

D = 2 log 2 n + 3

Therefore, the hardware requirements of the scheme are as follows:

A P C P = A A D D 1 + A M U X + A A D D 2 + A A D D 3 = 23 n + ( 15 2 ) log 2 n + 3

A M E P = 2 ( A A N D ) = 2

A O D P = 2 ( A A N D ) = 2

A O C P = A A D D 4 + A A D D 5 + A A D D 6 = 63 n + 14

The estimated delay of the scheme will be as follows:

D P C P = D A D D 1 + D A D D 2 + D A D D 3 = 4 log 2 n + 5

A M E P = 2 ( A A N D ) = 2

A O D P = 2 ( A A N D ) = 2

D O C P = D A D D 4 + A A D D 7 + A A D D 8 = 9 g a t e s

Now, in order to make an effective comparison, the proposed scheme is divided into two: Proposed Scheme I for when the OCP is not included in the comparison and Proposed Scheme II for the OCP being included in the comparison. The delay of the OCP overrides the delay of the delays of the MEP and the ODP if Proposed Scheme II is consider since they will all be computed in parallel and the critical path in that case will be dictated by the OCP. The area for the PCP and the MEP is double for two numbers X and Y but this is not the case for the delay of the two numbers since they are computed in parallel. Thus, the total area and delay of the proposed schemes are:

A T O T A L ( I ) = 2 A P C P + 2 A M E P + A O D P = 46 n + 15 log 2 n + 10

D T O T A L ( I ) = D P C P + D M E P = 4 log 2 n + 7

and,

A T O T A L ( I I ) = 2 A P C P + 2 A M E P + A O D P + A O C P = 109 n + 15 log 2 n + 24

D T O T A L ( I I ) = D P C P + D O C P = 4 log 2 n + 16

5. Numerical Illustrations

This subsection presents numerical illustrations of the proposed scheme.

Checking overflow in the sum of 49 and 21 using RNS moduli set {3, 4, 5}

X = 49 = ( 4 , 1 , 1 ) R N S 5 | 4 | 3 = ( 100 , 01 , 01 ) R N S 101 | 100 | 11

Y = 21 = ( 1 , 1 , 0 ) R N S 5 | 4 | 3 = ( 001 , 01 , 00 ) R N S 101 | 100 | 11

Z = ( ( 100 , 01 , 01 ) + ( 001 , 01 , 00 ) ) R N S 101 | 100 | 11 = ( 000 , 10 , 01 ) R N S 101 | 100 | 11

A reverse conversion of ( 000 , 10 , 01 ) R N S 101 | 100 | 11 will result in the decimal number 10. Whilst the sum of the decimal numbers 49 and 21 is 70 which is obvious of overflow occurring.

Checking for RNS overflow using the proposed technique

e 2 ( 49 ) = | 01 100 | 100 = 001

e 3 ( 49 ) = | ( 01 01 ) ( 10 ) 01 | 11 = | 01 | 11 = 10 = 2 2 2

which implies, β ( 49 ) = 1 from (11).

Also,

e 2 ( 21 ) = | 01 + | 001 | 100 | 100 = | 01 + 11 | 100 = 000

e 3 ( 21 ) = | ( 11 01 ) ( 10 ) 11 | 11 = | 100 11 | 11 = 01 = 2 2 3

But e 2 ( 21 ) = 000 , which implies β ( 21 ) = 0 from (11).

Therefore, from (13) o v e r f l o w = λ and needs further processing.

Since e 3 ( 49 ) + e 3 ( 21 ) = 10 + 01 = 11 > 2 2 2 , the scheme detects overflow occurring after processing.

Correction unit

Z = ( 100 + 001 ) + ( 01 + 00 ) ( 101 ) + ( 10 + 01 ) ( 101 ) ( 100 ) = 1000110 = ( 70 ) d e c i m a l

Checking overflow in the sum of 10 and 11 using RNS moduli set {3, 4, 5}

X = 49 = ( 4 , 1 , 1 ) R N S 5 | 4 | 3 = ( 100 , 01 , 01 ) R N S 101 | 100 | 11

Y = 11 = ( 1 , 3 , 2 ) R N S 5 | 4 | 3 = ( 001 , 11 , 10 ) R N S 101 | 100 | 11

Z = ( ( 000 , 10 , 01 ) + ( 001 , 11 , 10 ) ) R N S 101 | 100 | 11 = ( 001 , 01 , 00 ) R N S 101 | 100 | 11

RNS to decimal conversion of ( 001 , 11 , 10 ) R N S 101 | 100 | 11 will result in the decimal number 21, which is correct result of 10 + 11.

Checking for RNS overflow using the proposed algorithm

e 2 ( 10 ) = | 10 000 | 100 = 10 = 2 2 2

e 3 ( 10 ) = | ( 01 000 ) ( 10 ) 10 | 11 = | 10 10 | 11 = 00 < 2 2 3

which implies, β ( 10 ) = 0 since e 3 ( 10 ) = 00 < 2 2 3 , from (11).

Also,

e 2 ( 11 ) = | 11 + | 001 | 100 | 100 = | 11 + 11 | 100 = 10 = 2 2 2

e 3 ( 11 ) = | ( 10 001 ) ( 10 ) 10 | 11 = | 10 10 | 11 = 00 < 2 2 3

this implies, β ( 11 ) = 0 since e 3 ( 10 ) = 00 < 2 2 3 , from (11).

Thus, from (13) o v e r f l o w = 0 , which implies no overflow has occurred according to the proposed scheme after processing.

Correction unit

Z = ( 000 + 001 ) + ( 10 + 10 ) ( 101 ) + ( 00 + 00 ) ( 101 ) ( 100 ) = 010101 = ( 21 ) d e c i m a l

6. Performance Evaluation

The performance of the proposed scheme is compared to schemes in [3] and [8] ; the scheme in [8] does not contain a correction unit; the scheme by [3] has a correction unit but is not included in the comparison. And so both schemes do not have the correction component in the comparison. Table 1 shows the analysis of the proposed scheme with that of similar state-of-the art schemes.

As shown in Table 1, the proposed scheme for detecting overflow (Proposed Scheme I) in the given moduli set is very cheap in terms of hardware resources

Table 1. Area, delay comparison.

and faster than the scheme by [8] but requires a little hardware resources than the scheme by [3] albeit slower than the Proposed Scheme I. However, the complete proposed scheme (Proposed Scheme II) for detecting and correcting overflow requires more hardware resources than the other compared schemes but faster than both schemes by [3] and [8] .

Clearly, Proposed Scheme I completely outperforms the similar state-of-the-art scheme by [8] for detecting overflow, but the trust of this work is to detect and correct overflow anytime it occurs; in so doing it has made tremendous gains in speed as shown in Table 1.

Table 2 shows a detailed analysis of the complexities and delay of the proposed scheme with that of the similar state-of-the-art schemes.

Table 2 reveals interesting results theoretically, from the analysis it is clear that the Proposed Scheme I requires less resources than what is required by [8] . From the table, smaller values of n shows that Proposed Scheme II requires more resources than that by [8] but drastically improves upon this requirements up to over 51% better than [8] for higher values of n (i.e. n > 4), this is clearly shown in the graph in Figure 5. The analysis from the table also shows that whilst for smaller values of n (say n = 1), the Proposed Scheme I is better than the scheme by [3] in terms of hardware resources, it tends to require up to about 18% resources more than that by [3] .

From Figure 5, the scheme by [8] sharply increases for higher values of n followed by the Proposed Scheme II whilst the scheme by [3] requires the lesser resources. Regarding the delay, the proposed schemes (Proposed I and Proposed II) completely outperforms both schemes by up to over 35% than the scheme by [8] and over 90% faster than the scheme by [3] as shown in Table 2 and in Figure 5. It is worth noting that whiles the scheme by [3] performs better in terms of hardware resources, it tends to be the worst performer for speed and the

Table 2. Area, delay analysis for various values of n.

Figure 5. Graphs of area and delay analysis of the various compared schemes.

percentage difference shows that Proposed I is more efficient. It is clear from the graphs that in terms of delay, the scheme in [3] sharply increases with increasing values of n whiles the marginal increase of the rest of the schemes are minimal.

7. Conclusion

Detecting overflow in RNS arithmetic computations is very important but can be difficult, more so, if it has to be corrected. In this paper, an ingenious technique of detecting overflow by use of the MRC method through magnitude evaluation as well correcting the overflow when it occurs was presented. This technique did not require full reverse conversion but used the MRDs to evaluate the sign of a number to detect the occurrence of overflow. With this technique, the correct value of the sum of two numbers is guaranteed whether overflow occurred or not. The scheme has been demonstrated theoretically to be very fast than similar-state-of-the-art scheme but required a little more hardware resources. However, the Proposed Scheme I, which is the one without the correction component completely outperformed the scheme in [8] in terms of both area and delay requirements. Also, results from Table 2 and Figure 5 showed that for higher values of n, the Proposed Scheme II also outperformed the scheme by [8] . Future works will focus on simulating the theoretical results and implementing it on FPGA boards.

Cite this paper: Agbedemnab, P. , Akobre, S. and Bankas, E. (2018) An Efficient Overflow Detection and Correction Scheme in RNS Addition through Magnitude Evaluation. Journal of Computer and Communications, 6, 15-29. doi: 10.4236/jcc.2018.610002.
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