New Current Mode Lossy Integrator Employing CDDITA

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1. Introduction

Active RC Integrator is an extremely versatile circuit element that is employed in development and synthesis of numerous analog signal processing as well as generation circuits that include active filters, quadrature oscillators, waveform generators and many more. Various voltage or current mode integrator circuits based on traditional and modern active components has been proposed in literature. An OP-AMP based integrator was proposed in [1] . Some current conveyor (CCII) based integrator were proposed in [2] [3] [4] [5] [6] . Differential voltage current conveyor (DVCC) was also proposed in literature [7] . Some integrator circuits employing modern active elements like current differential buffered amplifier (CDBA) [8] , multiplication mode current conveyor (MMCC) [9] , current controlled current differential buffered amplifier (CCCDBA) [10] , differential difference current conveyor (DDCC) [11] , current differential transconductance amplifier (CDTA) [12] , current follower transconductance amplifier (CFTA) [13] , CCCCTA [14] and current feedback operational amplifier (CFOA) [15] have been proposed in the literature available till date.

But the circuit configurations available with us possess few disadvantages like: 1) they uses greater than 1 active element, 2) greater than 1 passive element, 3) floating capacitors are used which increases chip area, 4) no electronic tenability, 5) matching constraint required, 6) poor non ideal performance, 7) exclusive current output at very high impedance terminal is unavailability (in case of CM integrator).

Hence, the goal of this manuscript is to remove disadvantages mentioned above, hence it possess following advantages:

1) Only one CDDITA is used;

2) Just one capacitor is used;

3) Realization is purely free of resistor;

4) Grounded capacitor used, reduces chip area;

5) Gain is electronically tunable;

6) Better performance in non ideal case;

7) Current output signal at high impedance port is available.

CDDITA is new generation ABB and its idea was proposed in [16] . It is an extension of CDTA which has been a popular ABB in last decade. The electrical symbol of CDDITA is shown in Figure 1. It has two virtually grounded low input impedance terminals P and N, two high impedance intermediate terminals Z and V and two high impedance output terminals X+ and X−.

The behavioral model of CDDITA is shown in Figure 2, which illustrates that input stage is a current differencing unit and the output stage is an OTA.

The voltage current relationships between different ports of CDDITA can be given by following equation set:

${V}_{P}={V}_{n}=0$ (1)

${I}_{Z}=\left({I}_{P}-{I}_{N}\right)$ (2)

${I}_{X+}={g}_{m}\left({V}_{Z}-{V}_{V}\right)$ (3)

${I}_{X-}=-{g}_{m}\left({V}_{Z}-{V}_{V}\right)$ (4)

The CMOS realization of CDDITA has been shown in Figure 3.

The applications of CDDITA in analog signal processing/signal generation have been proposed in [17] [18] .

2. Proposed Current-Mode Integrator

The circuit of lossy integrator proposed is shown in Figure 4.

Figure 1. Block diagram of CDDITA.

Figure 2. Behavioral model of CDDITA.

Figure 3. CMOS implementation of CDDITA.

Figure 4. Proposed CM lossy Integrator.

Through proper analysis of circuit following expression is yielded the for output current;

$\frac{{I}_{out}}{{I}_{in}}=\frac{1}{1+\frac{sC}{{g}_{m}}}$ (5)

From Equation (5), it becomes clear that the gain of proposed integrator can be tuned electronically by g_{m1}, which is adjusted by bias currents of CDDITA. Output current “I_{out}” is explicitly available at high impedance “X−” port is shown in Figure 3. Hence, there is no additional need of follower is to use this output.

3. Non-Ideal Analysis and Sensitivity Calculations

Under non-ideal condition the CDDITA is defined by following equations of VDTA modified as

${I}_{Z}=\left({\alpha}_{p}{I}_{P}-{\alpha}_{n}{I}_{N}\right)$ (6)

${I}_{X+}={\beta}_{\text{+}}{g}_{m}\left({V}_{Z}-{V}_{V}\right)$ (7)

${I}_{X-}=-{\beta}_{-}{g}_{m}\left({V}_{Z}-{V}_{V}\right)$ (8)

where “
${\beta}_{\text{+}}$ ” and “
${\beta}_{-}$ ” are the trans-conductance error gains and “α_{p}” and “α_{n}” are errors in current transfer. These values are just slightly less than that of unity.

The current output transfer function of the presented paper under the influence of ideal conditions is given as

$\frac{{I}_{out}}{{I}_{in}}=\frac{1}{\frac{{\alpha}_{n}{\beta}_{+}}{{\alpha}_{p}{\beta}_{-}}+\frac{sC}{{g}_{m}{\alpha}_{p}{\beta}_{-}}}$ (9)

It is clear from Equation (9) that even; the proposed configuration has an ability to simulate an ideal CM integrator under the non-ideal conditions, with adjustable tunable gain. So, the nature of presented circuit remains unaffected in the non-ideal conditions.

4. Simulation Results

The presented circuit is verifying by simulating it by employing CMOS CDDITA (shown in Figure 3) with ±3 V DC supply voltage. All the biasing currents of CDDITA are chosen as 100 µA and the value of capacitor “C” is selected as 0.1 nF. To study the input output relation a rectangular input current signal (shown in Figure 5) of ±0.5 mA is used. The output current (I_{out}) is shown in Figure 6.

Figure 5. Input rectangular current pulse of amplitude ±0.5 mA and duration 4 µs (Iinput).

Figure 6. Output triangular current pulse (Ioutput).

5. Conclusion

A CDDITA based current mode lossy integrator circuit that uses single CDDITA and grounded capacitor has been presented in this manuscript. The proposed circuit has following features: no requirement of any resistor, electronically controllable gain and explicit current mode (CM) output at a high impedance port that is suitable for cascading and no requirement of component matching constraint. The designed circuit configuration shows good non-ideal behavior and even in that conditions the circuit can simulate a lossless CM integrator. The analysis has been successfully verified by PSPICE simulation using TSMC CMOS of 0.18 μm process parameters. For simulation purpose CMOS CDDITA has been used with biasing current of 100 µA and supply voltage of ±3 V DC.

Acknowledgements

This research is supported by the “Young Faculty Research Fellowship and Research/Contingency Grant” to Jamia Millia Islamia, under “Visvesvaraya PhD Scheme for Electronics and IT” in 2015-16.

Conflicts of Interest

The authors declare no conflicts of interest regarding the publication of this paper.

Nomenclature

V_{P}: Voltage at “P” terminal

V_{N}: Voltage at “N” terminal

V_{Z}: Voltage at “Z” terminal

V_{V}: Voltage at “V” terminal

I_{P}: Current at “P” terminal

I_{N}: Current at “N” terminal

I_{Z}: Current at “Z” terminal

I_{in}: Input current

I_{out}: Output current

g_{m}: Transconductance of CDDITA

α, β: Current gain errors

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