Implementation of sinusoidal oscillators and active biquadratic filters has become important modern analog active building blocks that have been introduced in  , and UVC is one of them which is emerging as a very flexible and versatile building block for analog signal processing and has been used earlier for realizing a number of functions. SRCOs play an important role in control systems, signal processing, communication, and instrumentation and measurement systems  -  . The applications, advantages, and usefulness of UVC have now been recognized in the realization of filters, in inductance simulation and in the realization of sinusoidal oscillator  -  . In ref.  , authors have been presented third-order quadrature oscillator using two second generation current conveyors, a UVC, three capacitors and three resistors. However, to the best of the knowledge and belief of the author, none of the SRCOs using single UVC has yet been presented in the literature so far. Therefore, the purpose of this paper is to present a new SRCO using a single UVC, two capacitors and three resistors. The proposed structure offers (1) independent control of both frequency of oscillation and, condition of oscillation (2) low passive sensitivities. The validity of the proposed SRCO has been confirmed by SPICE simulation using 0.18 µm TSMC process parameters.
2. New Oscillator Configuration
The symbolic notation and equivalent circuit model of UVC are shown in Figure 1(a) and Figure 1(b) respectively. The UVC is a 6-port active element with one voltage input x, two difference current inputs (y+, y−), two mutually inverse voltage outputs (z+, z−), and one auxiliary port w. The UVC can be described by the following set of equations.
The circuit of proposed SRCO is drawn in Figure 2.
Figure 1. (a) Symbolic notation of UVC; (b) Equivalent circuit model of UVC  .
Figure 2. Proposed SRCO using single UVC.
Routine circuit analysis (assuming ideal UVC) of Figure 2 yields following expressions for characteristic Equation (CE) is given as:
Thus, the condition of oscillation (CO) and frequency of oscillation (FO) are given by
3. Non-Ideal Analysis and Sensitivity Performance
Taking into account the non-idealities of UVC, the relationship between the port voltages and currents is shown by the hybrid matrix:
where and , for . Here and , represent the current and voltage tracking errors of the UVC respectively. The parasitic present on the low impedance ports (y+, y−, z+, z−) are quite low as compared to the resistances on the other ports (w and x)  . After considering the non-idealities of the UVC, given by the hybrid matrix of Equation (6), the characteristic Equation (CE), CO and FO are given as:
The various sensitivities of FO can be found as
In the ideal case, the various sensitivities of ω0 with respect to R1, R2, C1 and C2 are given as
To confirm the validity of the presented SRCO, the circuit was simulated using SPICE. The voltage and current values selected for CMOS implementation of UVC are ±1.9 V and 100 µA, respectively. The passive elements were chosen as C1 = C2 = lnF, R1 = R2 = 2.4 kΩ and R3 = 2.331 kΩ. The transient and steady state response of the proposed SRCO for the selected passive components are shown in Figure 3 and Figure 4 respectively. The SPICE simulated frequency response of the SRCO is shown in Figure 5. CMOS implementation of universal voltage conveyor is shown in Figure 6 and the W/L ratios of transistors used in Figure 6 are given in Table 1  . CMOS UVC was implemented 0.18 μm TSMC CMOS model parameters  .
A new voltage-mode single-resistance controlled sinusoidal oscillator employing single UVC has been proposed. The presented SRCO circuit employs single UVC, two capacitors and three resistors. The presented configuration offers (1) independent control of frequency of oscillation can be controlled by resistance
Figure 3. Transient response of the proposed SRCO.
Figure 4. Steady state response of the proposed SRCO.
Figure 5. Frequency spectrum of the proposed SRCO.
Figure 6. Implementation of CMOS structure of UVC, VDD = −VSS = 1.9 V, Io = 100 µA.
Table 1. The aspect ratios (W/L) of transistors used in Figure 6.
R2 and condition of oscillation can be adjusted by resistance R3, (2) low passive sensitivities. Simulation results using 0.18 μm TSMC CMOS technology have been presented to confirm the workability of the proposed new SRCO. This paper thus added a new application configuration to the existing repertoire of UVC based application circuits. For future one can reduce the passive elements or transistors in the device (UVC).
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