Back
 CS  Vol.2 No.4 , October 2011
Polymorphic Computing: Definition, Trends, and a New Agent-Based Architecture
Abstract: Polymorphic computing is widely seen as next evolutionary step in designing advanced computing architectures. This paper presents a brief history of reconfigurable and polymorphic computing, and highlights the recent trends and challenges. A novel polymorphic architecture featuring programmable memory event triggers and a new concept of control agents is proposed. This architecture can provide dynamic load balancing, distributed control, separated memory and processing fabrics, configurable memory blocks, and task-optimized computation.
Cite this paper: nullD. Hentrich, E. Oruklu and J. Saniie, "Polymorphic Computing: Definition, Trends, and a New Agent-Based Architecture," Circuits and Systems, Vol. 2 No. 4, 2011, pp. 358-364. doi: 10.4236/cs.2011.24049.
References

[1]   D. Harris, “Skew-Tolerant Circuit Design,” Morgan Kaufmann Publishers, Waltham, 2001.

[2]   G. Estrin, “Organization of Computer Systems—The Fixed Plus Variable Structure Computer,” Proceedings of the Western Joint Computer Conference, New York, 3-5 May 1960, pp. 33-40.

[3]   G. Estrin, “Reconfigurable Computer Origins: The UCLA Fixed-Plus Variable (F+V) Structure Computer,” IEEE Annals of the History of Computing, Vol. 24, No. 4, 2002, pp. 3-9. doi:10.1109/MAHC.2002.1114865

[4]   M. A. Baker and V. J. Coli, “The PAL20RA10 Story— The Customization of a Standard Product,” IEEE Micro, Vol. 6, No. 5, 1986, pp. 45-60. doi:10.1109/MM.1986.304713

[5]   R. Freeman, Configurable Electrical Circuit Having Configurable Logic Elements and Configurable Interconnects, US Patent No. 4,870,302, 26 September 1989.

[6]   A. Agarwal, “Raw Computation,” Scientific American, Vol. 281, No. 2, pp. 60-63. doi:10.1038/scientificamerican0899-60

[7]   M. B. Taylor, et al., “The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs,” IEEE Micro, Vol. 22, No. 2, 2002, pp. 25-35. doi:10.1109/MM.2002.997877

[8]   R. Ho, K. W. Mai and M. A. Horowitz, “The Future of Wires,” Proceedings of the IEEE, Vol. 89, No. 4, 2001, pp. 490-504. doi:10.1109/5.920580

[9]   K. Mai, T. Paaske, N. Jayasena, R. Ho, W. J. Dally and M. Horowitz, “Smart Memories: A Modular Reconfigurable Architecture,” Proceedings of the 27th International Symposium on Computer Architecture, Vancouver, 14 June 2000, pp. 161-171.

[10]   A. Firoozshahian, A. Solomatnikov, O. Shacham, Z. Asgar, S. Richardson, C. Kozyrakis and M. Horowitz, “A Memory System Design Framework: Creating Smart Memories,” Proceedings of the 36th Annual International Symposium on Computer Architecture, New York, 2009, pp. 406-417.

[11]   M. Herlihy and J. E. B. Moss, “Transactional Memory: Architectural Support for Lock-Free Data Structures,” Proceedings of the 20th Annual Symposium on Computer Architecture, San Diego, 16-19 May 1993, pp. 289-300. doi:10.1109/ISCA.1993.698569

[12]   D. Burger, S. W. Keckler, K. S. McKinley, M. Dahlin, L. K. John, C. Lin, C. R. Moore, J. Burrill, R. G. McDonald and W. Yoder, “Scaling to the End of Silicon with EDGE Architectures,” IEEE Computer, Vol. 37, No. 7, 2004, pp. 44-55.

[13]   R. McDonald, D. Burger, S.W. Keckler, K. Sankaralingam and R. Nagarajan, “TRIPS Processor Reference Manual,” Technical Report, Department of Computer Sciences, The University of Texas at Austin, Austin, 2005.

[14]   M. Gebhart, B. A. Maher, K. E. Coons, J. Diamond, P. Gratz, M. Marino, N. Ranganathan, B. Robatmili, A. Smith, J. Burrill, S. W. Keckler, D. Burger and K. S. McKinley, “An Evaluation of the TRIPS Computer System (Extended Technical Report),” Technical Report TR-08-31, Department of Computer Sciences, The University of Texas at Austin, Austin, 2008.

[15]   J. B. Dennis and D. P. Misunas, “A Preliminary Architecture for a Basic Dataflow Processor,” Proceedings of the 2nd Annual Symposium on Computer Architecture New York, 1975, pp. 126-132. doi:10.1145/642089.642111

[16]   J. Draper, J. Sondeen, S. Mediratta and I. Kim, “Implementation of a 32-Bit RISC Processor for the Data-Intensive Architecture Processing-in Memory Chip,” Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, San Jose, 17-19 July 2002, pp. 163-172. doi:10.1109/ASAP.2002.1030716

[17]   J. Draper, J. Sondeen and C. W. Kang, “Implementation of a 256-Bit Wide-Word PROCESSOr for the Data-Intensive Architecture (DIVA) Processing in Memory (PIM) Chip,” Proceedings of the 28th European Solid-State Circuits Conference, Florence, 2002, pp. 77-80.

[18]   J. Draper, J. Chame, M. Hall, C. Steele, T. Barrett, J. La-Coss, J. Granacki, J. Shin, C. Chen, C. W. Kang, I. Kim and G. Daglikoca, “The Architecture of the DIVA Processing-in-Memory Chip,” Proceedings of the 16th International Conference on Supercomputing 2002, New York, 2002, pp. 14-25.

[19]   J. Granacki, and M. Vahey,” MONARCH: A Morphable Networked Micro-ARCHitecture,” Technical Report, USC/Information Sciences Institute and Raytheon, Marina del Rey, May 2003.

[20]   J. J. Granacki, “MONARCH: Next Generation SoC (Supercomputer on a Chip),” Technical Report, USC/Information Sciences Institute, Marina del Rey, February 2005.

[21]   K. Prager, L. Lewins, M. Vahey and G. Groves, “World’s First Polymorphic Computer—MONARCH,” 11th Annual High Performance Embedded Computing Workshop 2007, 2007. http://www.ll.mit.edu/HPEC/agendas/proc07/agenda.html

[22]   R. Hartenstein, “A Decade of Reconfigurable Computing: A Visionary Retrospective,” Proceedings of the Conference on Design, Automation and Test in Europe 2001, Munich, 13-16 March 2001, pp. 642-649. doi:10.1109/DATE.2001.915091

 
 
Top