Seemingly endless trend of downscaling CMOS technology features in almost linear manner according to the Moore’s law , as it was a rather common practice during several previous decades, has enabled the semiconductor industry to fit an ever-in- creasing number of devices per unit area and also achieve higher performance expressed as unit of energy (watt) spent in performing computational tasks. Various research directions have been mostly addressing possible ways how to achieve even a greater scaling of the technology features in order to push the actual integration level further beyond the existing boundaries. Nevertheless, the existence of physical limits to this growth is generally recognized today: the electronics-based technologies cannot be scaled down beyond certain dimensions that are inherently defined by some physical constraints . Nowadays, it is possible to identify a lot of diverse application areas where a digital circuit with the inherent ability to perform a set of different functions at particular moments in time may prove to be a very efficient means of solution. Obviously the most immediate approach, how to address this specific need, is to design as many different circuits as the overall number of functions that are actually needed in a given situation. As a next step involved within the execution flow, individual outputs of these circuits are switched in such a way that only the presently required function will be taken into account. However, the main drawback behind this conception, and its essential limitation as well, will emerge in direct connection with the overall size of the resulting implementation on the circuit level that needs to be placed into a target area of a restricted dimensions.
Recent advancements within the field of digital design techniques and components for digital circuits provide a vital evidence that yet another feasible strategy may be employed―area and time-efficient circuit design based on utilization of individual structural elements exhibiting multifunctional nature . In this case, the entity of multifunctional circuit is devised as a compact structure involving set of multifunc- tional components, where their mutual, low-level interconnection scheme remains untouched in all allowable operating modes and only the active function of these components is expected to change intentionally.
A special case related to these multifunctional circuits is based on adoption of polymorphic electronics approach . Such circuits typically change their function in accordance to the actual state of a target operating environment, which is represented by a physical quantity with notable influence on some of the physical parameters of electronic structures?power supply voltage level, voltage amplitude of a signal, tem- perature, etc. In addition, no configuration network with a global scope or dedicated input pins of these components are required . It’s important to point out that change of the active function, which is executed by the polymorphic circuit, takes place immediately.
The structure of this paper is organized as follows: the opening section explains basic aspects of multifunctional circuits. Section II is briefly explaining key aspects behind polymorphic electronics and the benefits to be obtained when using ambipolar components. Brief review of selected polymorphic circuit synthesis methods can be found in section III. Then, ambipolar transistor model is shown in section IV together with specification of basic components. Finally, section V provides the conclusion.
2. Polymorphic Electronics
The notion of polymorphic electronics  determines, in its own essence, a standalone category of reconfigurable circuits, which represents a highly appealing prospect how to implement all the required functional properties in a resource-efficient way. In the case of these circuits assuming the principles of polymorphic electronics, various modifications in the key physical characteristics of building components (e.g. in a transistor’s operation point, usage of ambipolar charge carrier conductivity) are predominantly involved behind the change of their behaviour as a straight response to the influence of external stimuli?temperature, power supply voltage, light intensity, special signal, etc. However, the structure of the circuit itself remains unchanged on the interconnection level for all the intended functions.
2.1. Survey of Existing Polymorphic Gates
It is pertinent that the availability of suitable building components can be identified as one of the key prerequisites enabling the practical deployment of polymorphic circuits. As it is demonstrated in Table 1, there already exist a number of polymorphic gates
Table 1. Overview of existing polymorphic gates.
which are implementing various functions. These gates were mostly constructed by means of using certain variation of conventional CMOS fabrication process. Main drawback in this case can be attributed precisely to the fact that it is necessary to use transistors with different channel width and length dimensions in order to achieve the polymorphic behaviour. This observation also explains the reason why individual transistors in such circuitry may also operate in linear mode instead of adhering to the switching mode only. As a consequence steady current flow through such gates leads to significant rise in power consumption.
2.2. Benefits of Amnipolarity
Therefore unconventional approach to the construction of polymorphic gates using technologies such as transistors with ambipolar characteristics  is highly desirable. Such gates contains less transistors and also operate exclusively in switching mode. An example of ambipolar polymorphic gate is given on Figure 1. This gate exhibits NOR function when M1 and M2 are in N-mode and M3 and M4 are in P-mode. When all transistors change the polarity, NAND function is exhibited by the gate. The polarity of transistors, and by this the function of the gate, is controlled by power?polarity of voltages V0 & V1.
2.3. Synthesis of Polymorphic Circuits
Nowadays, design of polymorphic circuits is performed almost exclusively at a gate level. Results of practical experiments in this domain indicate that meaningful poly- morphic circuits always include a combination of several polymorphic gates alongside the selection of ordinary gates. In most situations only one type of polymorphic gate (e.g. NAND/NOR) is employed in the whole design procedure . The overall design efficiency (in terms of circuit size or speed) could be further improved if a more diverse selection of polymorphic gates (other types besides NAND/NOR variant as well) is taken into account. However, it would be definitely paid by a more complicated synthesis process due to the state space growth. Let’s also note that none of the existing synthesis methods takes into account yet the polymorphic gates based on ambipolar behaviour.
Figure 1. Polymorphic NAND/NOR gate using ambipolar transistors.
2.4. Evolutionary Approach
Digital circuit synthesis and optimization techniques based on thoughtful exploitation of convenient evolutionary-inspired paradigms, as demonstrated by Sekanina  (and before initially suggested e.g. by Miller ), could establish a way how to achieve a rather unconventional but, at the same time, interesting and useful solution. Needless to say, also the original concept of polymorphic electronics emerged virtually as a side effect of evolutionary design experiments . Almost all polymorphic circuits, more complex than just a few gates, have been designed using Carthesian Genetic Progra- mming (CGP)  till now.
2.5. Conventional Methods
The first method from this cathegory involves the so-called polymorphic multiplexing . For each function, a digital circuit is synthesized and the outputs of these circuits are then multiplexed by a polymorphic multiplexor. The structure of a circuit designed by this method shows a relatively low optimality. However, possible workaround towards the desirable improvement dwells in the partial sharing of some logic resources between individual functions.
In addition to the already introduced method, Gajda  proposed a method of polymorphic circuit synthesis utilizing binary decision diagrams (BDD). The method is called PolyBDD. Its core is based on Multi-terminal BDD (MTBDD), which is an extension of binary decision diagrams. MTBDD representation, which is created for desired functions F1 and F2, is further converted into a circuit, where the nodes assume the role of multiplexers and the terminals are replaced by a proper polymorphic sub- circuit according to the previously assigned integer number.
3. Ambipolar Transistor Model and Components
This section is dealing with a definition of fundamental model for ambipolar transistors, which are important means for describing operation of polymorphic gates. Figure 2 shows an example of ambipolar transistor model created by means of utilizing conventional silicon MOSFET transistors. For the construction of such a model, transistors with terminated substrate would be preferable. Unfortunately, such transis- tors are rare, so the model was created from the standard P-type and N-type transistors.
Figure 2. Basic model of an ambipolar transistor.
Each instance of the unipolar MOSFET transistor has an integrated body diode where its unwanted influence must be eliminated by anti-serial connection of diodes D1 and D2.
The function of this model is explained in details within Table 2. Its columns D, S, G denotes the individual terminals of the transistor model; their values are + or -, which corresponds to the supply voltage polarity (Vcc, GND). Then, columns D1, D2 simply denote anti-serial diodes from transistor model and have values of F (forward direction) or R (reverse direction). Columns T1 and T2 are related to transistors from the same model. If a value is ON, the transistor is closed (current flows through the transistor), while OFF signature denotes that transistor is open (and therefore current cannot flow across this element). The last column depicts the behavior of the model where HiZ represents the high impedance state (model is “tri-stated”). “Close” option simply means that the model is closed and the conductive pat his available for current.
Ambipolar Inverter and Negation/Identity Gate
The simplest gate formed from an ambipolar transistors is an inverter. Unlike to conventional CMOS-based one, when the ambipolar transistors are used, both are of the same type. It means that the transistors will autonomously select their operating mode with respect to their deployment inside a given circuit. This makes the ambipolar inverter resistant to power supply polarity change―if the Vcc and GND are swapped, the type of transistors will change.
Figure 3 above shows the configuration of polymorphic inverter model, which is using simulated ambipolar transistors. Input of the inverter is connected to GND (logic L level). The output is expected to reach the level of Vcc. Results obtained from measurement are depicted on Figure 4. Situation, when the input signal is assigned to H level (close to Vcc) is very similar. The only difference is that output of the inverter is constantly staying at L level. Finally, negation/identity gate is shown on Figure 5.
Figure 3. Evaluation setup of ambipolar polymorphic inverter-input connected to GND (logil level L close to amplitude of 0 V).
Table 2. Operating states of an ambipolar transistor model.
Figure 4. Measured characteristics of ambipolar inverter, input attached to L.
Figure 5. Ambipolar polymorphic gate with the function of negation/idnetity.
It is fortunate that we have at hand a property called ambipolarity. This important property allows to design efficient implementation of various polymorphic gates in comparison with conventional approach. Further steps will include the adoption of a platform with configurable matrix of Si-NW transistors  for truly ambipolar solution.
This work was generously supported by the internal grant Architecture of parallel and embedded computer systems (no. FIT-S-14-2297) and by national COST grant Unconventional Design Techniques for Intrinsic Reconfiguration of Digital Circuits: From Materials to Implementation (no. LD14055).
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