Received 22 April 2016; accepted 10 May 2016; published 18 August 2016
Over the past decades, semiconductor technology has provided enormous enhancements in systems characteristics such as power consumption, speed, reliability and production cost. Such improvements came into practice mainly due to the continuous miniaturization of device dimensions in the fabrication process  . This incessant down scaling of devices leveraged the integration of more circuitry on a single chip producing complex hardware systems. However, this down scaling cannot take place forever. There are many factors that limit the down scaling of transistors such as the minimum dimensions that can be fabricated and increase in the off-state power consumption due to high leakage currents   . Hence, innovations are required to allow for the continued growth in the complexity of hardware systems. One of these innovations is the memristors and memristive devices  .
Memristors existences were theoretically predicted in 1971 by Chua  . In 2008, Hewlett Packard (HP) physically realized the memristor  . A memristor is a resistive switch that produces either a high resistance or a low resistance depending on the polarity of the applied voltage, i.e., the direction of current flow   . Figure 1 shows the symbol and polarity of the memristor.
Memristors are mainly used in memories. In memories, memristors are used to represent logic states, i.e., the resistance of a memristor is used to represent logic 0 or logic 1. Memristors are not only used in memory systems. They are also used to design neuromorphic systems, analog circuits and digital logic circuits  . For instance, in  , memristors are used to design digital logic circuits. In  , a logic family is described, namely, Memristor Ratioed Logic (MRL). MRL uses memristors that are integrated with CMOS inverters to perform Boolean NAND and NOR functions. One of the main advantages of using memristors in evaluating logic is that it saves physical area and therefore increases logic density.
As of any other device, memristors are prone to defects. Numerous research efforts took place in testing memristor-based memory systems. In   , different fault models were proposed.  , proposed two DfT schemes for testing memristors using these fault models and the conventional March test was used, in which a fixed pattern of reads and writes are applied to each memory cell to detect faults in that cell. This method (tests one cell at a time) is time consuming for large memories. Therefore, testing multiple transistors at the same time was needed. This was done by using divide-and-conquer testing technique proposed in  . However, this technique does not consider sneak-paths (unwanted current flow) in crossbar memories. In  , a sneak-path testing scheme was proposed to test multiple memristors simultaneously using sneak-path currents. In  , a new design was proposed to overcome the issue of sneak path currents in memristor crossbar memories. The design is comprised of one access transistor and one memristor (1T1R). Fault models are proposed in  , based on electrical defects. A March Test is proposed to cover all the defined faults.
All the aforementioned research efforts focus on testing memory systems designed using memristors. This work is concerned about testing digital logic gates implemented using memristors.
To the best of the authors’ knowledge, the production testing of MRL has not been tackled yet in the literature. In this paper, catastrophic faults in memristors and transistors are investigated in the context of production testing. The minimum test set is obtained and then compared to that of the conventional stuck-at fault model. It will be shown that while testing MRL NAND/NOR gates, some test escapes might take place. Hence, two solutions are proposed to face this issue. The first is applying scaled input voltages and the second is to alter the switching threshold of the inverter. Additionally, it will be shown that test sequence and speed should be taken into consideration.
The rest of the paper is organized as follows. Section 2 provides a description of MRL logic family. Section 3 is devoted to the testing of the MRL gates that includes faults in the memristors and transistors. Conclusions are mentioned in Section 4.
2. Memristor Ratioed Logic (MRL) Family
In this section, explanation of the MRL logic family is provided. In  , MRL is used to design two-input NAND and NOR Boolean functions. The memristors are used to perform the AND and OR functionalities, while a standard CMOS inverter is used to obtain their complements. In  , the TEAM (ThrEshold Adaptive Memristor) model was used.
Figure 1. Memristor symbol. Thick black line on the left represents the polarity of the device. If current flows into the device, resistance of the memristor decreases and vice versa.
Two-input AND and OR logic gates consists of two memristors connected in series at opposite polarities as shown in Figure 2(a) and Figure 2(b), respectively. The memristors are used as computational elements to evaluate logic. On one end of the memristors terminals the inputs A and B are applied, while the common node of the memristors is the output node labeled Vout,AND and Vout,OR. The CMOS inverter is added then for reasons mentioned later in this section.
In the AND logic gate, when the current flows into the memristors, the resistance of the memristors increases and reaches Roff eventually. On the other hand, if the current flows out of the memristors, the resistance of the memristors decreases and reaches Ron eventually. The OR logic gate has the exact opposite behavior of the AND gate as opposite polarity is used.
In the following explanation, 0 V is used to represent logic “0” and 1V is used to represent logic “1”. AND and OR logic gates behave similarly when identical inputs are applied, i.e., AB = 00 or AB = 11. When these inputs are applied there is no current flow through the memristors. Hence, there is no voltage drop between the inputs. Therefore, the output voltage Vout,AND and Vout,OR are similar to the input voltage. In the case where the inputs are different, i.e., AB = 01 or 10, current flows from the higher input voltage terminal to the lower. This changes the resistance of the two memristive devices.
In the AND logic gate, consider the input vector AB = 10. For this case, the current flows out of the memristor labeled R1 in Figure 2(a). R1 reaches Roff by the end of the computational process. Simultaneously, the current flows into the memristor labeled R2 in Figure 2(a) and R2 reaches Ron towards the end of the logic evaluation. The output voltage Vout,AND is a voltage divider between the two memristors, and is therefore
Consider the same scenario AB = 10 for the OR logic gate, where opposite polarity is used. Therefore, the resistance of the memristors behave in the exact opposite way of the AND logic gate and the output voltage Vout,OR is therefore
It should be noted that the initial resistance of both memristors does not affect the functionality. However, it affects the delay of computation when both inputs are different  . A standard CMOS inverter is added for two main reasons. First, since the AND and OR functions are non-inverting, a complete logic structure is achieved by connecting the output node to a CMOS inverter. In addition, memristive devices lack signal restoration, i.e., the output voltage levels will degrade if these logic gates are cascaded for several levels  .
3. Production Testing of NAND and NOR
This section investigates production testing for catastrophic faults in the MRL NAND and NOR logic gates shown in Figure 2(a) and Figure 2(b). MRL uses memristors and transistors to build logic gates. Therefore, faults that occur in both memristors and transistors are considered.
Figure 2. Schematic of (a) two-input MRL NAND (b) two-input MRL NOR.
In this paper the TEAM model is used as this model was used by  in the proposed designs. The ELDO simulator from Mentor Graphics is used in this study and the technology is the 45 nm CMOS technology.
The memristor stuck at fault model proposed in  is used. This fault model assumes that the resistance of the memristor will remain stuck at either Ron or Roff irrespective of the applied voltage across its terminals. According to the TEAM model parameters, Ron is 100W and Roff is 200 KW. In addition, the transistor five-fault model proposed in  is used, as it is one of the most commonly used fault models. The five-fault model consists of five faults per transistor which are: Drain-Source short circuit (DS), Gate-Drain short circuit (GD), Gate-Source short circuit (GS), Open Drain (OD) and Open Source (OS). It was shown in  that open circuit faults can be modeled by inserting a 250 MW (or more) resistance in the 45 nm technology, while short circuit faults are modeled by inserting a 10 W resistance. Faults are injected one at a time as in  . For every fault, the circuit output is compared to the fault-free output. A fault is considered detected if the output is different from the fault- free case.
3.1. Memristor Faults
In this section, memristor faults are considered for both the NAND and NOR logic gates. The standard CMOS inverter used in Figure 2(a) and Figure 2(b) has a switching threshold voltage (VM) of 0.5 V. Vout,AND and Vout,OR (input nodes of the inverter) may be affected by noise that is taken as 5% of the supply voltage (1 V), i.e., 0.05 V as in  . Hence any input voltage to the inverter that falls between 0.45 V and 0.55 V is considered to be in the undefined region. For the NAND and NOR logic gates, it is observed that, due to faults in the memristors, the output voltage Vout,AND and Vout,OR falls in the undefined region for some input vectors. Therefore, it is considered here that these input vectors that produce an output in the undefined region, cannot be used as test vectors.
For the NAND logic gate, consider for example, the fault R1 stuck at Roff; it is clear from Figure 3 that all test vectors produce the correct output except the test vector AB = 01. This input vector produces a 0.5 V at the Vout,AND node, that falls in the undefined region. A similar argument exists for AB = 10 as the circuit is symmetric.
The explanation of this result is as follows. Applying the test vector “01” forces R1 to switch to Ron and R2 should switch to Roff by the end of the computation process. However, due to the fault, R1 does not switch to Ron and is stuck at Roff. Hence the output voltage Vout,AND is therefore 0.5 V from (3).
Figure 3. Test results for R1 stuck at Roff for the NAND gate.
Likewise, the same issue of output voltages falling in the undefined region occurs in the NOR logic gate. Therefore, there are two different proposed solutions to face the aforementioned issue as shown in the coming subsections.
3.1.1. Scaled Input Voltages
The first proposed solution is applying scaled input voltages to the inputs of the logic gates to detect all memristor faults. For the NAND logic gate, 0.33 V is used to represent logic low “0” while keeping logic high “1” represented by 1 V. This forces the output voltage Vout,AND to be 0.67 V (midpoint between 0.33 V and 1 V) for the same fault (R1 à Roff), which is interpreted by the CMOS inverter as logic high “1” (0.67 V is not in the undefined region); so the NAND output is logic low “0” and the fault is detected. Table 1 shows the test results for the NAND gate where logic low “0” is 0.33 V and logic high “1” is 1 V. Note that in Table 1, “D” indicates a detected fault while “U” indicates undetected fault. Also R à Ron indicates that the resistance of the memristor is stuck at Ron and R à Roff indicates that the resistance of the memristor is stuck at Roff.
For the NOR gate, the solution is keeping 0 V to represent the logic low “0” while logic high “1” should be represented by 0.67 V. Table 2 shows the test results for the MRL NOR gate
3.1.2. Changing the Switching Threshold of the Inverter
The second proposed solution is changing VM of the inverters, by carefully sizing the PMOS and NMOS transistors. For the NAND logic gate, the inverter is designed to have VM of 0.35 V. Consider the same fault R1 à Roff for the same input vector AB = 01; this fault causes the input of the inverter Vout,AND to be 0.5 V which is interpreted by the inverter as logic high “1” so the NAND output is logic low “0” and the fault is detected. The test results are identical to those shown in Table 1. For the NOR logic gate, the inverter is designed to have VM of 0.65 V. The test results are identical to those shown in Table 2. Table 3 shows a summary of the VM and the undefined region of the three different CMOS inverters.
Figure 4 shows the test results for the fault previously discussed (R1 stuck at Roff). It is clearly shown that the 0.5V value does not appear anymore and the fault is detected using the test vector 01.
Figure 4. Test results for R1 stuck at Roff for the NAND gate using the two proposed solutions.
Table 1. MRL NAND test results.
Table 2. MRL NOR test results.
Table 3.Summary of VM and the undefined region of the three different inverters.
3.2. Resistive Open Faults
In this subsection, detection of resistive open faults is shown. It is observed that detecting resistive open faults depend on the speed of test vector application and the order of application of the test vectors. It was shown in  that detecting resistive open faults depends on the speed of test vector application. For the NAND logic gate in Figure 2(a), consider, for example, the fault M1 OD, i.e., resistive open in transistor M1. For the input vectors 01 or 10, an RC circuit is established between the supply voltage Vdd and the NAND output node. R is RM1, which is the equivalent ON resistance of the PMOS transistor M1 in series with Rop, which is the injected fault. C represents the overhead capacitance. In this case the delay of the inverter can be estimated by (4) as in  :
Therefore, if the test speed is very slow, i.e., enough time is given for logic evaluation and the fault will not be detected. This applies for both NAND and NOR gates. Additionally, it was shown in  that testing resistive open faults in the CMOS NAND logic gate depends on the order of test vector application. It is concluded from  , that although the minimum test set includes only three test vectors, namely 01, 10 and 11, four input vectors have to be applied. For example, a possible test sequence might be 11, 01, 11, 10.
Likewise, detecting resistive open faults in NAND and NOR MRL family depends on the order of test vectors application. The coming two subsections discuss the test sequence needed for full fault coverage in NAND and NOR MRL family.
3.2.1. Detection of Resistive Open Faults for the Scaled Input Voltages Proposal
It is mentioned earlier that input voltages are scaled to detect all memristor faults. It is found that detecting open faults depends on the order of test vector application. For instance, consider the fault M2 OD/OS for the NAND logic gate, i.e., resistive open in transistor M2 in Figure 2(a). This fault isolates the NAND output from the ground voltage. So if the input vector applied is 11 the output node will also not be connected to the supply because this turns transistor M1 off. The output then is floating and retains its previous logic state as in  . In order to detect this fault, an initializing vector activating the pull up PMOS transistor M1 must be applied which is 01 or 10 in this case. Applying these test vectors 11 pulls up the output of the NAND gate to “1”. After applying the initializing vector, the test vector 11 is applied. This keeps the output of the NAND gate in the floating state and will retain its previous logic state, which is “1” and hence the fault is detected. Table 4 shows test results of detecting open faults in transistors M1 and M2 for the MRL NAND gate. Unlike the previous fault, open faults in M1 do not require a specific sequence to be detected and can be detected by either 01 or 10. M1 OD/OS merely cuts the path for the supply voltage and, accordingly, M1 is unable to pull up the output node to “1”. When 01 or 10 is applied, bearing in mind that “0” is 0.33 V, 0.33 V (higher than the threshold of the transistor) is transmitted to the input of the inverter, switches M2 ON and the output node is pulled to ground. Hence, the fault is detected.
The same explanation could be given for resistive opens in the NOR MRL logic gates. However, different test vectors are used with specific sequence as shown in Table 5.
3.2.2. Detection of Resistive Open Faults for the Different Switching Thresholds of the Inverter Proposal
It is mentioned earlier that changing VM of the inverter is needed to detect all memristor faults. Order of test vector application is required for full fault coverage in this proposed solution. For instance, consider the fault M1 OD/OS for the NAND logic gate, i.e., resistive open in transistor M1 in Figure 2(a). This fault isolates the NAND output from the supply voltage. So if the input vector applied is 01 or 10 the output node will also not be connected to ground because this turns transistor M2 off. The output then is floating and retains its previous logic state as in  . In order to detect this fault, an initializing vector activating the pull down NMOS transistor M1 must be applied which is 11 in this case. Applying the test vector 11 pulls down the output of the NAND gate to “0”. After applying the initializing vector, any of the other two test vectors 01 or 10 could be applied. This keeps the output of the NAND gate in the floating state and will retain its previous logic state, which is “0” and hence the fault is detected. The same explanation could be given for other resistive opens in the NAND and NOR MRL logic gates. Table 6 shows the test sequence required to detect open faults in transistors M1 and M2 for the MRL NAND gate.
The same explanation could be given for resistive opens in the NOR MRL logic gates. However, different test vectors are used with specific sequence as shown in Table 7.
Table 4. Test sequence/vectors to detect open faults in MRL NAND using scaled input voltages.
Table 5. Test sequence/vectors to detect open faults in MRL NOR using scaled input voltages.
Table 6. Test sequence to detect open faults in MRL NAND using low VM inverter.
Table 7. Test sequence to detect open faults in MRL NOR using high VM inverter.
3.3. Resistive Short Faults
For the NAND MRL, consider, for instance, the fault M1 DS, this forces the output node to always be logic high “1” as the node is shorted to the supply. Therefore, this fault is only detected by the test vector AB = 11, where the output in the fault free scenario should have been logic low “0”. Figure 5 shows the test result of this fault. Similar analysis could be given for short faults in the NOR MRL gate.
It is concluded from the test results shown above that, for the two proposals, the minimum test set required is identical to that obtained from the conventional single stuck-at fault model. However, it was shown that the order of applying the test vectors is important. A possible test pattern that obtains 100% fault coverage in NAND MRL gate is (10, 11, 01). This is a major difference between MRL NAND and CMOS NAND in that, despite both gates requiring the same three test vectors for full coverage, MRL requires a sequence of three vectors while CMOS requires a sequence of four vectors. A similar argument is valid for the NOR gate. It is also concluded that detecting resistive open faults in MRL NAND/NOR gate depends on the test speed.
Figure 5. NAND M1 DS fault.
Table 8. Resistive short faults test results in MRL NAND.
Table 9. Resistive short faults test results in MRL NOR.
Memristors have been physically characterized in 2008 by HP. One of the main advantages of using memristors in memories, analog circuits, neuromorphic systems and digital circuits is its area occupancy. Memristors and CMOS inverters are integrated with each other to realize logic gates such as NAND and NOR. This design logic family is called MRL. The main advantage of this logic family is that it saves physical area and therefore increases logic density, which allows the increase of system complexity. Hence, it is important to test these gates efficiently.
In this study, the TEAM model and the 45 nm CMOS technology were used. The memristor stuck at fault model and the five-fault model are considered. Faults are injected one at a time. A fault is considered detected if the output is different from the fault-free output scenario.
During the testing of memristor faults, the input of the inverter falls in the undefined region and this can lead to test escapes. Therefore, two solutions were proposed to face this challenge. The first is to apply scaled input voltages and the second is to change the VM of the inverter. It is shown that the minimum test set obtained in order to obtain full coverage for MRL NAND/NOR gates is identical to that obtained from the conventional single stuck-at fault model. However, the speed of applying the test vectors and the test order should be taken into account. Unlike CMOS NAND/NOR that requires a sequence of four vectors for 100% fault coverage, MRL NAND/NOR requires a sequence of only three test vectors.
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