vity in NIR detectors [15] . In designing photodetectors, and in particular uncooled detectors, it is crucial to ensure that the dark current remains at an acceptable level generally considered to be 1 µA or less [16] . Measures to potentially limit dark/leakage current include enhancing device surface and/or sidewall passivation, improving crystalline quality of material layers and adjusting the doping levels, and using optimized growth methods. It is notable that lowering band gap in Ge by incorporating tensile strain reduces the density of states for holes, leading to decreased intrinsic carrier density that can also contribute to lower reverse dark current in detector devices.

3. Device Fabrication Process

3.1. Growth/Fabrication Process Overview

We have fabricated Ge based PIN photodetector devices on 300 mm (12 inch) diameter Si wafers at the Colleges of Nanoscale Science and Engineering (CNSE), State University of New York Polytechnic Institute (SUNY Poly), located in Albany, NY. This facility offers industry-leading wafer processing technologies and high-end CMOS fabrication capabilities in fully equipped 300 mm cleanrooms with large-area Si/Ge tools, enabling epitaxial growth of Ge for the development of room temperature operation photodetectors that can be heterogeneously integrated with CMOS circuitry for significant cost reduction.

The deposition of Ge in the development of the normal-incidence PIN Ge photodetectors is accomplished through a two-step growth process intended to reduce threading dislocations arising primarily from lattice mismatch between the Si and Ge to enable higher quality Ge films with consequently lower dark current [17] . This growth technique involves initial low temperature deposition of Ge to form a thin strain-relaxed seed layer, and successive high temperature growth to form a thicker absorbing film. All Ge depositions were performed using a 300 mm reduced-pressure chemical vapor deposition (RPCVD) system utilizing germane as the precursor and hydrogen as the carrier gas with typical reactor pressures in the range of 5 - 100 Torr. The RPCVD method provides high control of layer and multi-layer thicknesses, making it well suited for large-scale wafer fabrication.

3.2. Two-Step Growth Process

The first low temperature growth step involves fully planar homoepitaxial deposition of a relatively thin Ge p+ (boron) doped seed/buffer layer on a 300 mm Si wafer substrate at temperatures of 350˚C - 400˚C. At this relatively low growth temperature range intended to promote planar growth, the low surface diffusivity of Ge kinetically suppresses undesired three-dimensional Stranski-Krastanov islanding that can otherwise result from strain release [18] . By contrast, seed layer deposition at temperatures below 320˚C commonly leads to crystallographic defect formation, while that at temperatures above 400˚C can produce surface roughening due to the increased surface mobility of Ge [19] .

In the subsequent high temperature step of the growth process, a layer of intrinsic Ge serving as the absorption region is grown at 550˚C - 600˚C. This temperature range was chosen to ensure satisfactory deposition rates for smooth high crystal quality Ge films with sufficient tensile strain [18] . Due to the difference in thermal expansion coefficients between the Ge and underlying Si substrate as discussed previously, compressive stain is effected in this intrinsic layer upon cooling following the high temperature growth. The wafer was later annealed at 600˚C for 30 s. A flowchart illustrating the sequential device fabrication process steps is given in Figure 1.

Figure 1. Flowchart illustrating device fabrication process including two-step growth.

3.3. Final Device Fabrication Steps

Following the two-step growth of the Ge seed and intrinsic layers, upper n+ regions were formed through ion implantation of phosphorus (P) into the underlying intrinsic layer. The basic steps comprising this process are described as follows: A layer of SiO2 was deposited above the i-Ge layer, intended to isolate states at the interface between it and the signal carrying layers as well as reduce traps that could contribute to leakage current [20] . Circular windows were then opened in this oxide to the underlying i-Ge using reactive-ion etching (RIE), in which a thin 20 nm layer of screen oxide was deposited. Next, P was ion-implanted at 60 keV through the screen oxide layer in the portions exposed by the windows, forming n+ regions under these openings. (The processed 300 mm wafer was subjected to various degrees of P ion implantation, producing four different n+ region doping levels in its quadrants ranging from 5 × 1018 cm−3 to 1 × 1020 cm−3.) The screen oxide was then etched away.

After formation of the n+ regions, diffusion barrier layers composed of tantalum nitride (TaN), which is thermodynamically stable with respect to copper (Cu) and has low electrical resistance, were implemented in these openings above the n+ regions. Finally, low resistance Cu contacts were deposited in the windows above the TaN, and chemical-mechanical polishing (CMP) was applied to the surface of the wafer/devices.

4. Device Characterization

4.1. Structural Characteristics of Devices

Various methods were utilized to characterize the material and structural properties first of the epitaxial growth and then of the fabricated detector devices. High-resolution X-ray diffraction (HRXRD) and optical microscopy demonstrated that grown epitaxial films were over-relaxed (i.e, tensile strained) and composed of essentially pure Ge, having very smooth and practically defect-free topologies when the seed layers had thicknesses of at least 100 nm. By contrast, for Ge intrinsic layers grown on 22 nm thick seed layers a surface defect density of approximately 2000 cm−2 was observed [21] .

Secondary ion mass spectroscopy (SIMS) was likewise utilized to analyze the constituent elements in the detector devices down to the Si substrate. Data representing off-contact depth analysis are plotted Figure 2(a); these results show the intrinsic and seed layers of the device to be predominately comprised of Ge, and boron doping concentration of ~5 × 1018 cm−3 in the latter. Through-contact SIMS data were likewise acquired, shown in Figure 2(b), evidencing Ge and phosphorus underneath the contact.

4.2. Detector Electrical Performance

For testing the electrical characteristics of the fabricated photodetector devices, we utilized a probe station, electrical source-measurement unit (Keithley 2400 SourceMeter), and 10 mW broadband fiber-coupled tungsten- halogen light source providing high intensity over the NIR (~1000 - 1700 nm) spectrum. The dark current and

(a)(b)

Figure 2. (a) “Off-contact” SIMS analysis data measured down through SiO2 and the underlying PIN detector layer structure. (b) “Through-con- tact” SIMS analysis data measured down through Cu contact and the underlying PIN detector layer structure.

photocurrent I-V curves are shown in Figure 3(a). For a device (different from the one used for SIMS data) with n+ region P doping level of 5 × 1019 cm−3, the measured dark current at −1 V was approximately 0.6 nA, which is low compared to minimal dark current results reported to date for Ge/SiGe photodetectors [22] - [24] . For 100 μm square devices, this corresponds to a dark current density of 6 μA/cm2. Furthermore, the dark current remained relatively steady even as the magnitude of the reverse bias was increased, rising only slightly to 0.7 nA and 1.1 nA, at −2 V and −4 V, respectively.

The photocurrent at −1 V for this device was 168 nA, over two orders of magnitude greater than the dark current, which increased marginally with greater negative bias. The zero bias dark photocurrent was 138 nA, above 80% the value of that produced at −1 V. In addition, the maximum forward-to-reverse current ratio measured at ±1 V was ~2 × 105 for a 1019 cm−3 n+-doped device.

Additionally, temporal characterization of the photoresponse for the PIN photodetector devices was performed while modulating the incident front-surface illumination on and off. Figure 3(b) shows the plotted photoresponse for a device with n+ region doping of 5 × 1019 cm−3. It is seen that the dark current with no NIR

(a) (b)

Figure 3. (a) Dark current and photocurrent I-V curves for detector device (dark current data partially extrapolated to compensate for measurement uncertainty); (b) time-dependent photoresponse measured while periodically modulating the incident NIR radiation source on and off.

Table 1. Comparison of I-V results for four devices having different n+ region (P) doping concentrations.

exposure was below 1 nA. Under illumination, the measured photocurrent rose to above 100 nA, with sharp high/low transitions.

Table 1 presents a comparison of the I-V measurements and corresponding calculated values procured from fabricated photodetector devices characterized by different n+ region doping levels. In these devices, the n-type regions must have sufficient doping (e.g., >1019 cm−3) to enable the electron transport between the metal and the semiconductor to be in the field emission regime for the creation of low-resistance ohmic contacts [25] . The ratio of photocurrent to dark current (“Photo/Dark”), for which both are measured at −1 V bias, basically constitutes the current gain of the device samples under illumination. In addition, “IF/IR (Dark) Ratio” is the forward-to-reverse current ratio measured at ±1 V bias, where higher ratios (greater asymmetry) indicate better rectifying behavior for the PIN devices. Based on these results, the 5 × 1019 cm−3 device, which meets the above mentioned criteria for ohmic contacts, had the best overall performance including the highest photocurrent and gain, and thus is considered to have an optimal doping concentration for these types of PIN devices. The lower performance for the highest doped device may be attributed in part to less photons reaching the absorption layer due to free-carrier absorption, which increases substantially with higher doping.

5. Summary and Conclusions

Ge provides a low-cost alternative material system for developing uncooled photodetectors operating at NIR wavelengths using CMOS based fabrication processes. PIN photodetectors incorporating epitaxial Ge layers on large-area 300 mm Si substrates using leading-edge facilities and growth techniques have been developed. We have utilized a two-step low/high temperature fabrication process to reduce dark current as well as introduce tensile stain. Characterization of the material properties of fabricated detector devices evidenced high quality epitaxial growth of pure Ge. In addition, electrical characterization of devices with various n+ region doping concentrations demonstrated low dark currents down to ~0.6 nA and above two orders of magnitude enhancement in current under broadband illumination at −1 V bias, with 5 × 1019 cm−3 identified to be the optimal n+ doping level. Arrays developed based on such NIR photodetectors exhibiting low dark current could potentially benefit applications such as muzzle flash or hostile fire detection for which low noise background is desired.

6. Future Work

Each fabricated wafer contains hundreds of different devices which we characterize via SIMS and electrical measurements. Due to the difficulty of maintaining control over Ge etching, further investigation mainly employing transmission electron microscopy (TEM) is needed in order to confirm the uniformity of the Ge in different devices across the wafer.

Acknowledgements

This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA). The views, opinions, and/or findings expressed are those of the authors and should not be interpreted as repress- enting the official views or policies of the Department of Defense or the US Government.

Cite this paper
Rouse, C. , Zeller, J. , Efstathiadis, H. , Haldar, P. , Lewis, J. , Dhar, N. , Wijewarnasuriya, P. , Puri, Y. and Sood, A. (2016) Development of Low Dark Current SiGe Near-Infrared PIN Photodetectors on 300 mm Silicon Wafers. Optics and Photonics Journal, 6, 61-68. doi: 10.4236/opj.2016.65009.
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