Synthesis of Time-to-Amplitude Converter by Mean CoeVolution with Adaptive Parameters

ABSTRACT

The challenging task to synthesize automatically a time-to-amplitude converter, which unites by its functionality several digital circuits, has been successfully solved with the help of a novel methodology. The proposed approach is based on a paradigm according to which the substructures are regarded as additional mutation types and when ranged with other mutations form a new adaptive individual-level mutation technique. This mutation approach led to the discovery of an original coevolution strategy that is characterized by very low selection rates. Parallel island-model evolution has been running in a hybrid competitive-cooperative interaction throughout two incremental stages. The adaptive population size is applied for synchronization of the parallel evolutions.

The challenging task to synthesize automatically a time-to-amplitude converter, which unites by its functionality several digital circuits, has been successfully solved with the help of a novel methodology. The proposed approach is based on a paradigm according to which the substructures are regarded as additional mutation types and when ranged with other mutations form a new adaptive individual-level mutation technique. This mutation approach led to the discovery of an original coevolution strategy that is characterized by very low selection rates. Parallel island-model evolution has been running in a hybrid competitive-cooperative interaction throughout two incremental stages. The adaptive population size is applied for synchronization of the parallel evolutions.

Cite this paper

nullY. Sapargaliyev and T. Kalganova, "Synthesis of Time-to-Amplitude Converter by Mean CoeVolution with Adaptive Parameters,"*Journal of Software Engineering and Applications*, Vol. 4 No. 8, 2011, pp. 447-464. doi: 10.4236/jsea.2011.48052.

nullY. Sapargaliyev and T. Kalganova, "Synthesis of Time-to-Amplitude Converter by Mean CoeVolution with Adaptive Parameters,"

References

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[12] J. Wang, K. Je, Y. Lee and H. Chong, “Using Reconfigurable Architecture-Based Intrinsic Incremental Evolution to Evolve a Character Classification System,” In: Y. Hao, J. Liu, Y.-P. Wang, Y.-M. Cheung, H. Yin, L. Jiao, J. Ma and Y.-C. Jiao, Eds., CIS 2005. LNCS (LNAI), Springer, Heidelberg, Vol. 3801, 2005, pp. 216-223.

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[14] C. Mattiussi and D. Floreano, “Analog Genetic Encoding for the Evolution of Circuits and Networks, “IEEE Trans. on Evolutionary Computation, Vol. 11, 2007, pp. 596-607. doi:10.1109/TEVC.2006.886801

[15] W. Feng, L. Yuanxiang, L. Kangshun and L. Zhiyi, “A New Circuit Representation Method for Analog Circuit Design Automation,” IEEE World Congress on Computational Intelligence, IEEE Press, Hong Kong, 2008. doi:10.1109/CEC.2008.4631059

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[19] A. Ngom, “Parallel Evolution Strategy on Grids for the Protein Threading Problem,” Journal of Parallel and Distributed Computing, Vol. 66, No. 12, 2006, pp.1489-1502. doi:10.1016/j.jpdc.2006.08.005

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[21] J. Lohn, W. Kraus and G. Haith, “Comparing a Coevolutionary Genetic Algorithm for Multiobjective Optimization,” Proceedings of the Evolutionary Computation, CEC’02. Proceedings of the 2002 Congress, 12-17 May 2002, pp. 1157-1162.

[22] B. Liu, Y. Wang, Z. Yu, L. Liu, M. Li, Z. Wang, J. Lu and F. Fernandez, “Analog Circuit Optimization System Based on Hybrid Evolutionary Algorithms,” Integration, the VLSI Journal, Vol. 42, No. 2, February 2009, pp. 137-148.

[23] K. Maneeratana, K. Boonlong and N. Chaiyaratana, “Multi-Objective Optimisation by Co-Operative Co-Evo- lution,” In: X. Yao, et al., Eds, Parallel Problem Solving from Nature—PPSN VIII, Lecture Notes in Computer Science, Vol. 3242, September 2004, Springer-Verlag, Birmingham, pp. 772-781. doi:10.1007/978-3-540-30217-9_78

[24] R. Zebulum, M. Vellasco and M. Pacheco, “Variable Length Representation in Evolutionary Electronics,” Evolutionary Computation, Vol. 8, No. 1, March 2000, pp. 93-120. doi:10.1162/106365600568112

[25] A. Thompson, “Artificial Evolution in the Physical World,” In: Gomi, Ed., Evolutionary Robotics, AAI Books, 1997, pp. 101-125.

[26] I. Guerra-Gomez, E. Tlelo-Cuautle, Luis G. de la Fraga, T. McConaghy and G. Gielen, “Sizing Mixed-Mode Circuits by Multi-Objective Evolutionary Algorithms,” Proceedings of IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Seattle, 2010, pp. 813-817.

[27] Feodosia State Optical Factory, “The Artillery Quantum Rangefinder (Online),” February 2011. http://fkoz.feodosia.com.ua/main3.phtml?link=23

[28] J. Hu, E. D. Goodman, K. Seo and M. Pei, “Adaptive Hierar-Chical Fair Competition (AHFC) Model for Parallel Evolutionary Algorithms,” Proceedings of the Genetic and Evolutionary Computation Conference (GECCO), New York, 2002, pp. 772-779.

[29] A. Petrowski, “A Clearing Procedure as a Niching Method for Genetic Algorithms,” Proceedings of the IEEE International Conference on Evolutionary Computation, 1996, pp. 798-803.

[1] Y. Sapargaliyev and T. Kalganova, “On Comparison of Constrained and Unconstrained Evolutions in Analogue Electronics on the Example of LC Low-Pass Filters,” IEICE Transactions on Electronics, Vol. E89-C, No. 12, 2006, pp. 1920-1927.

[2] T. Kalganova, “Bidirectional Incremental Evolution in Evolvable Hardware,” Proceedings of 2nd NASA/DoD Workshop Evolvable Hardware, 13-15 July 2000, pp. 65-74.

[3] Y. Sapargaliyev and T. Kalganova, “Challenging the Evolutionary Strategy to Synthesis Analogue Computational Circuits,” Journal of Software Engineering and Applications, Vol. 3, No. 11, November 2010, pp. 1032-1039.

[4] E. Stomeo, T. Kalganova and C. Lambert, “Mutation Rate for Evolvable Hardware,” International Conference on Computational Intelligence—ICCI 2005, Prague, Czech Republic, 26-28 August 2005, pp. 117-124.

[5] “Model 2145 Time to Amplitude Converter/Single Channel Analyzer,” Datasheet, Canberra Industries, Inc. heep://www.canberra.com/pdf/Products/Model-2145-SS-0226.pdf

[6] J. Shapiro, A. Prügel-Bennett and M. Rattray, “A Statistical Mechanical Formulation of the Dynamics of Genetic Algorithms,” Lecture Notes in Computer Science, Vol. 865, 1994, pp. 17-27.

[7] Y. Sapargaliyev and T. Kalganova, “Automated Synthesis of 8-Output Voltage Distributor using Incremental Evolution,” Proceedings of 2010 NASA/ESA Conference on Adaptive Hardware and Systems, IEEE, 15-18 June 2010, pp. 186-193.

[8] F. Herrera and M. Lozano, “Adaptive Genetic Operators Based on Coevolution with Fuzzy Behaviors,” IEEE Transactions on Evolutionary Computation, Vol. 5, No. 2, 2001, pp. 149-165. doi:10.1109/4235.918435

[9] J. R. Koza and D. Andre, “Evolution of Both the Architecture and the Sequence of Workperforming Steps of a Computer Program Using Genetic Programming with Architecture-Altering Operations,” In: P. Angeline and K. Kinnear, Eds., Advances in Genetic Programming, Vol. 2, 1996.

[10] T. B?ck, “The Interaction of Mutation Rate, Selection, and Adaptation within Genetic Algorithm,” In: R. M?nner and B. Manderick, Eds., Parallel Problem Solving from Nature 2, Elsevier, Amsterdam, The Netherlands, 1992, pp. 85-94.

[11] J. Torresen, “A Divide-and-Conquer Approach to Evolvable Hardware,” In: M. Sipper, D. Mange and A. Pérez-Uribe, Eds., ICES 1998, LNCS, Springer, Heidelberg, Vol. 1478, 1998, pp. 57-65.

[12] J. Wang, K. Je, Y. Lee and H. Chong, “Using Reconfigurable Architecture-Based Intrinsic Incremental Evolution to Evolve a Character Classification System,” In: Y. Hao, J. Liu, Y.-P. Wang, Y.-M. Cheung, H. Yin, L. Jiao, J. Ma and Y.-C. Jiao, Eds., CIS 2005. LNCS (LNAI), Springer, Heidelberg, Vol. 3801, 2005, pp. 216-223.

[13] J. Walker, K. V?lk, S. Smith and J. F. Miller, “Parallel Evolution Using Multi-Chromosome Cartesian Genetic Programming,” Genetic Programming and Evolvable Machines, Vol. 10, No. 4, 2009, pp. 417-445. doi:10.1007/s10710-009-9093-2

[14] C. Mattiussi and D. Floreano, “Analog Genetic Encoding for the Evolution of Circuits and Networks, “IEEE Trans. on Evolutionary Computation, Vol. 11, 2007, pp. 596-607. doi:10.1109/TEVC.2006.886801

[15] W. Feng, L. Yuanxiang, L. Kangshun and L. Zhiyi, “A New Circuit Representation Method for Analog Circuit Design Automation,” IEEE World Congress on Computational Intelligence, IEEE Press, Hong Kong, 2008. doi:10.1109/CEC.2008.4631059

[16] PSpice A/D Reference Guide, (includes PSpice A/D, PSpice A/D Basics, and Pspice. Product Version 15.7), Cadence, July 2006.

[17] J. Hu, E. D. Goodman, K. Seo and M. Pei, “Adaptive Hierar-Chical Fair Competition (AHFC) Model for Parallel Evolutionary Algorithms,” Proceedings of the Genetic and Evolutionary Computation Conference (GECCO), New York, 2002, pp. 772-779.

[18] R. Lohmann, “Application of Evolution Strategy in Parallel Populations,” In: H. P. Schwefel and R. M?anner, Parallel Problem Solving from Nature—Proceedings of 1st Workshop, (PPSN 1), Vol. 496 of Lecture Notes in Computer Science, Springer-Verlag, Berlin, 1991, pp. 198-208.

[19] A. Ngom, “Parallel Evolution Strategy on Grids for the Protein Threading Problem,” Journal of Parallel and Distributed Computing, Vol. 66, No. 12, 2006, pp.1489-1502. doi:10.1016/j.jpdc.2006.08.005

[20] L. Jostins, “A Comparison of Parallel Global Optimisation Algorithms for Reverse Engineering Gene Networks,” MPhil Thesis, University of Cambridge, Cambridge, 21 August 2008.

[21] J. Lohn, W. Kraus and G. Haith, “Comparing a Coevolutionary Genetic Algorithm for Multiobjective Optimization,” Proceedings of the Evolutionary Computation, CEC’02. Proceedings of the 2002 Congress, 12-17 May 2002, pp. 1157-1162.

[22] B. Liu, Y. Wang, Z. Yu, L. Liu, M. Li, Z. Wang, J. Lu and F. Fernandez, “Analog Circuit Optimization System Based on Hybrid Evolutionary Algorithms,” Integration, the VLSI Journal, Vol. 42, No. 2, February 2009, pp. 137-148.

[23] K. Maneeratana, K. Boonlong and N. Chaiyaratana, “Multi-Objective Optimisation by Co-Operative Co-Evo- lution,” In: X. Yao, et al., Eds, Parallel Problem Solving from Nature—PPSN VIII, Lecture Notes in Computer Science, Vol. 3242, September 2004, Springer-Verlag, Birmingham, pp. 772-781. doi:10.1007/978-3-540-30217-9_78

[24] R. Zebulum, M. Vellasco and M. Pacheco, “Variable Length Representation in Evolutionary Electronics,” Evolutionary Computation, Vol. 8, No. 1, March 2000, pp. 93-120. doi:10.1162/106365600568112

[25] A. Thompson, “Artificial Evolution in the Physical World,” In: Gomi, Ed., Evolutionary Robotics, AAI Books, 1997, pp. 101-125.

[26] I. Guerra-Gomez, E. Tlelo-Cuautle, Luis G. de la Fraga, T. McConaghy and G. Gielen, “Sizing Mixed-Mode Circuits by Multi-Objective Evolutionary Algorithms,” Proceedings of IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Seattle, 2010, pp. 813-817.

[27] Feodosia State Optical Factory, “The Artillery Quantum Rangefinder (Online),” February 2011. http://fkoz.feodosia.com.ua/main3.phtml?link=23

[28] J. Hu, E. D. Goodman, K. Seo and M. Pei, “Adaptive Hierar-Chical Fair Competition (AHFC) Model for Parallel Evolutionary Algorithms,” Proceedings of the Genetic and Evolutionary Computation Conference (GECCO), New York, 2002, pp. 772-779.

[29] A. Petrowski, “A Clearing Procedure as a Niching Method for Genetic Algorithms,” Proceedings of the IEEE International Conference on Evolutionary Computation, 1996, pp. 798-803.