Chip Design of a Low-Voltage Wideband Continuous-Time Sigma-Delta Modulator with DWA Technology for WiMAX Applications

ABSTRACT

This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.

This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.

Cite this paper

nullJ. Huang, Y. Lai, W. Lai and R. Liu, "Chip Design of a Low-Voltage Wideband Continuous-Time Sigma-Delta Modulator with DWA Technology for WiMAX Applications,"*Circuits and Systems*, Vol. 2 No. 3, 2011, pp. 201-209. doi: 10.4236/cs.2011.23029.

nullJ. Huang, Y. Lai, W. Lai and R. Liu, "Chip Design of a Low-Voltage Wideband Continuous-Time Sigma-Delta Modulator with DWA Technology for WiMAX Applications,"

References

[1] J. Yu and B. Zhao, “Continuous-Time Sigma-Delta Modulator Design for Low Power Communication Applications,” Proceedings of IEEE ASICON, October 2007, pp. 715-720.

[2] R. H. M. van Veldhoven, B. J. Minnis, H. A. Hegt and A. H. M. van Roermund, “A 3.3-mW ΣΔ Modulator for UMTS in 0.18-um CMOS with 70-dB Dynamic Range in 2-MHz Bandwidth,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, 2002, pp. 1645-1652. doi:10.1109/JSSC.2002.804329

[3] L. Dorrer, F. Kuttner, P. Greco, P. Torta and T. Hartig, “A 3-mW 74-dB SNR 2-MHz Continuous-Time Deltasigma ADC with a Tracking ADC Quantizer in 0.13-um CMOS,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 12, 2005, pp. 2416-2427. doi:10.1109/JSSC.2005.856282

[4] S. R. Norsworthy, R. Schreier and G. C. Temes, “Delta-Sigma Data Converters: Theory, Design and Simulation,” IEEE Press, New York, 1996.

[5] B. J. Farahani and M. Ismail, “Adaptive Sigma Delta ADC for WiMAX Fixed Point Wireless Applications,” IEEE Midwest Symposium on Circuits and Systems, Vol. 1, Covington, 7-10 August 2005, pp. 692-695.

[6] T. L. Brooks, D. H. Robertson, D. F. Kelly, A. D. Muro and S. W. Harston, “A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25 MHz Signal Bandwidth and 89 dB SNR,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 12, 1997, pp. 1896-1906. doi:10.1109/4.643648

[7] R. Jiang and T. Fiez, “A 14-bit Delta-Sigma ADC with 8X OSR and 4-MHz Conversion Bandwidth in A 0.18 um CMOS Process,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 1, 2004, pp. 63-74. doi:10.1109/JSSC.2003.820877

[8] A. Bosi, A. Panigada, G. Cesura and R. Castello, “An 80 MHz 4x Oversampled Cascaded ΔΣ-Pipelined ADC with 75 dB DR and 87 dB SFDR,” IEEE International Solid-State Circuits Conference, 2005, pp. 174-175.

[9] F. Munoz, K. Philips and A. Torralba, “A 4.7 mW 89.5 dB DR CT Complex DS ADC with Built-In LPF,” IEEE International Solid-State Circuits Conference, February 2005, pp. 500-501.

[10] J. A. Cherry and W. M. Snelgrove, “Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion,” Kluwer, Boston, 2000.

[11] S. Paton, A. D. Giandomenico, L. Hernandez, A. Wiesbauer, T. Potscher and M. Clara, “A 70-mW 300-MHz CMOS Continuous-Time ΣΔ ADC with 15-MHz Bandwidth and 11 Bits of Resolution,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 7, July 2004, pp. 1056-1063. doi:10.1109/JSSC.2004.829925

[12] G. Mitteregger, C. Ebner. S. Mechnig, T. Blon, C. Holu- igue and E. Romani, “A 20-mW 640-MHz CMOS Continuous-Time ΣΔ ADC with 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-Bit ENOB,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 12, 2006, pp. 2641-2649. doi:10.1109/JSSC.2006.884332

[13] S. Karthikeyan, S. Mortezapour, A. Tammineedi and E. Lee, “Low-Voltage Analog Circuit Design Based on Biased Inverting Opamp Configuration,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 47, No. 3, 2000, pp. 176-184. doi:10.1109/82.826743

[14] L. Lamarre, M. Louerat and A. Kaiser, “A Simple 3.8 mW, 300 MHz, 4-Bit Flash Analog-to-Digital Converter,” Proceedings of the SPIE, Vol. 5837, No. 51, 2005, pp. 825- 832. doi:10.1117/12.608343

[15] B. Razavi, “Principles of Data Conversion System Design,” IEEE Press, New York, 1995.

[16] J. Chen, S. Kurachi, S. Shen, H. Liu, T. Yoshimasu and Y. Suh, “A Low-Kickback-Noise Latched Comparator for High-Speed Flash Analog-to-Digital Converters,” Proceedings of IEEE ISCIT, Vol. 1, 12-14 October 2005, pp. 250-253.

[17] Z. Li and T. S. Fiez, “A 14-Bit Continuous-Time Deltasigma A/D Modulator with 2.5 MHz Signal Bandwidth,” IEEE Journal of Solid-State Circuits, Vol. 42, No. 9, 2007, pp. 1873-1883. doi:10.1109/JSSC.2007.903086

[18] J. Bastos, A. M. Marques, M. S. J. Steyaert and W. Sansen, “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 12, 1998, pp. 1959-1969. doi:10.1109/4.735536

[19] T. H. Kuo, K. D. Chen and H. R. Yeng, “A Wideband CMOS Sigma-Delta Modulator with Incremental Data Weighted Averaging,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 1, 2002, pp. 11-17. doi:10.1109/4.974541

[20] F. Gerfers, M. Ortmanns and Y. Manoli, “A 1.5-V 12-Bit Power-Efficient Continuous-Time Third-Order ΣΔ Modulator,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 8, 2003, pp. 1343-1352. doi:10.1109/JSSC.2003.814432

[21] L. J. Breems, R. Rutten and G. Wetzker, “A Cascaded Continuous-Time ΣΔ Modulator with 67-dB Dynamic Range in 10-MHz Bandwidth,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, 2004, pp. 2152-2160. doi:10.1109/JSSC.2004.836245

[22] S. D. Kulchycki, R. Trofin, K. Vleugels and B. A. Wooley, “A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, 2008, pp. 796-804. doi:10.1109/JSSC.2008.917499

[23] M. Anderson and L. Sundstrom, “Design and Measurement of a CT ΔΣ ADC with Switched-Capacitor Switched-Resistor Feedback,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 2, 2009, pp. 473-483. doi:10.1109/JSSC.2008.2010978

[24] A. Hart and S. P. Voinigescu, “A 1 GHz Bandwidth Low-Pass ΔΣ ADC with 20-50 GHz Adjustable Sampling Rate,” IEEE Journal of Solid- State Circuits, Vol. 44, No. 5, 2009, pp. 1401-1414. doi:10.1109/JSSC.2009.2015852

[1] J. Yu and B. Zhao, “Continuous-Time Sigma-Delta Modulator Design for Low Power Communication Applications,” Proceedings of IEEE ASICON, October 2007, pp. 715-720.

[2] R. H. M. van Veldhoven, B. J. Minnis, H. A. Hegt and A. H. M. van Roermund, “A 3.3-mW ΣΔ Modulator for UMTS in 0.18-um CMOS with 70-dB Dynamic Range in 2-MHz Bandwidth,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, 2002, pp. 1645-1652. doi:10.1109/JSSC.2002.804329

[3] L. Dorrer, F. Kuttner, P. Greco, P. Torta and T. Hartig, “A 3-mW 74-dB SNR 2-MHz Continuous-Time Deltasigma ADC with a Tracking ADC Quantizer in 0.13-um CMOS,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 12, 2005, pp. 2416-2427. doi:10.1109/JSSC.2005.856282

[4] S. R. Norsworthy, R. Schreier and G. C. Temes, “Delta-Sigma Data Converters: Theory, Design and Simulation,” IEEE Press, New York, 1996.

[5] B. J. Farahani and M. Ismail, “Adaptive Sigma Delta ADC for WiMAX Fixed Point Wireless Applications,” IEEE Midwest Symposium on Circuits and Systems, Vol. 1, Covington, 7-10 August 2005, pp. 692-695.

[6] T. L. Brooks, D. H. Robertson, D. F. Kelly, A. D. Muro and S. W. Harston, “A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25 MHz Signal Bandwidth and 89 dB SNR,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 12, 1997, pp. 1896-1906. doi:10.1109/4.643648

[7] R. Jiang and T. Fiez, “A 14-bit Delta-Sigma ADC with 8X OSR and 4-MHz Conversion Bandwidth in A 0.18 um CMOS Process,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 1, 2004, pp. 63-74. doi:10.1109/JSSC.2003.820877

[8] A. Bosi, A. Panigada, G. Cesura and R. Castello, “An 80 MHz 4x Oversampled Cascaded ΔΣ-Pipelined ADC with 75 dB DR and 87 dB SFDR,” IEEE International Solid-State Circuits Conference, 2005, pp. 174-175.

[9] F. Munoz, K. Philips and A. Torralba, “A 4.7 mW 89.5 dB DR CT Complex DS ADC with Built-In LPF,” IEEE International Solid-State Circuits Conference, February 2005, pp. 500-501.

[10] J. A. Cherry and W. M. Snelgrove, “Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion,” Kluwer, Boston, 2000.

[11] S. Paton, A. D. Giandomenico, L. Hernandez, A. Wiesbauer, T. Potscher and M. Clara, “A 70-mW 300-MHz CMOS Continuous-Time ΣΔ ADC with 15-MHz Bandwidth and 11 Bits of Resolution,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 7, July 2004, pp. 1056-1063. doi:10.1109/JSSC.2004.829925

[12] G. Mitteregger, C. Ebner. S. Mechnig, T. Blon, C. Holu- igue and E. Romani, “A 20-mW 640-MHz CMOS Continuous-Time ΣΔ ADC with 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-Bit ENOB,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 12, 2006, pp. 2641-2649. doi:10.1109/JSSC.2006.884332

[13] S. Karthikeyan, S. Mortezapour, A. Tammineedi and E. Lee, “Low-Voltage Analog Circuit Design Based on Biased Inverting Opamp Configuration,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 47, No. 3, 2000, pp. 176-184. doi:10.1109/82.826743

[14] L. Lamarre, M. Louerat and A. Kaiser, “A Simple 3.8 mW, 300 MHz, 4-Bit Flash Analog-to-Digital Converter,” Proceedings of the SPIE, Vol. 5837, No. 51, 2005, pp. 825- 832. doi:10.1117/12.608343

[15] B. Razavi, “Principles of Data Conversion System Design,” IEEE Press, New York, 1995.

[16] J. Chen, S. Kurachi, S. Shen, H. Liu, T. Yoshimasu and Y. Suh, “A Low-Kickback-Noise Latched Comparator for High-Speed Flash Analog-to-Digital Converters,” Proceedings of IEEE ISCIT, Vol. 1, 12-14 October 2005, pp. 250-253.

[17] Z. Li and T. S. Fiez, “A 14-Bit Continuous-Time Deltasigma A/D Modulator with 2.5 MHz Signal Bandwidth,” IEEE Journal of Solid-State Circuits, Vol. 42, No. 9, 2007, pp. 1873-1883. doi:10.1109/JSSC.2007.903086

[18] J. Bastos, A. M. Marques, M. S. J. Steyaert and W. Sansen, “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 12, 1998, pp. 1959-1969. doi:10.1109/4.735536

[19] T. H. Kuo, K. D. Chen and H. R. Yeng, “A Wideband CMOS Sigma-Delta Modulator with Incremental Data Weighted Averaging,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 1, 2002, pp. 11-17. doi:10.1109/4.974541

[20] F. Gerfers, M. Ortmanns and Y. Manoli, “A 1.5-V 12-Bit Power-Efficient Continuous-Time Third-Order ΣΔ Modulator,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 8, 2003, pp. 1343-1352. doi:10.1109/JSSC.2003.814432

[21] L. J. Breems, R. Rutten and G. Wetzker, “A Cascaded Continuous-Time ΣΔ Modulator with 67-dB Dynamic Range in 10-MHz Bandwidth,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, 2004, pp. 2152-2160. doi:10.1109/JSSC.2004.836245

[22] S. D. Kulchycki, R. Trofin, K. Vleugels and B. A. Wooley, “A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, 2008, pp. 796-804. doi:10.1109/JSSC.2008.917499

[23] M. Anderson and L. Sundstrom, “Design and Measurement of a CT ΔΣ ADC with Switched-Capacitor Switched-Resistor Feedback,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 2, 2009, pp. 473-483. doi:10.1109/JSSC.2008.2010978

[24] A. Hart and S. P. Voinigescu, “A 1 GHz Bandwidth Low-Pass ΔΣ ADC with 20-50 GHz Adjustable Sampling Rate,” IEEE Journal of Solid- State Circuits, Vol. 44, No. 5, 2009, pp. 1401-1414. doi:10.1109/JSSC.2009.2015852