With the rapid development of integrated circuits , low power consumption has become a constant pursuiting goal of the designer in chip design. As the memory almost takes up the area of the chip, reducing memory power consumption will significantly reduce the overall power consumption of the chip; according to ISSCC’s 2014 report about technology trends discussions, there two points of the super-low power SRAM design: 1) design a more effective static and dynamic power control circuit for each key module of SRAM; 2) ensure that in the case of the very low VDD min, SRAM can operating reliably and stably. This paper makes full use reliable of 8T cell, and the single-port sense amplifier has solved problems in the traditional 8T cell structure, making the new structure of the memory at a greater depth still maintain good performance and lower power consumption. Compared with the designed SRAM the SRAM generated by commercial compiler, as the performance loss at SS corner does not exceed 10%, the whole power consumption could be reduced by 54.2%, which can achieve a very good effect of low-power design.
 Nalam, S., Chandra, V., Pietrzyk, C., Aitken, R.C. and Calhoun, B.H. (2010) Asymmetric 6T SRAM with Two-Phase Write and Split Bitline Differential Sensing for Low Voltage Operation. Proc. 11th Int. Symp. Qual. Electron. Des. (ISQED), March 2010, 139-146. http://dx.doi.org/10.1109/isqed.2010.5450400
 Giridhar, B., Pinckney, N., Sylvester, D. and Blaauw, D. (2014) 13.7 A Reconfigurable Sense Amplifier with Auto- Zero Calibration and Pre-Amplification in 28 nm CMOS. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, February 2014, 242-243.
 Verma, N. and Chandrakasan, A.P. (2008) A High-Density 45 nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, February 2008, 380-621.