[1] PIETROBON S S. Implementation and performance of a turbo/ MAP decoder. Int. J. Satellite Communication, 1998, 16: 23-46.
[2] KAZA J, CHAKRABARTI C. Design and implementation of low-energy turbo decoders. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004, 12(9): 968-977.
[3] HAGH M, SALEHI M, ET AL. Implementation issues in turbo decoding for 3GPP FDD receiver. Wireless Personal Communi- cations, 2006, 39(2): 165-182.
[4] LEE D-S, PARK I.-C. Low-power log-MAP decoding based on reduced metric memory access. IEEE Transactions on Circuits and Systems, 2006, 53(6): 1244-1253.
[5] BOUTILLON E, GROSS W J, GULAK P G. VLSI architectures for the MAP algorithm. IEEE Transactions on Communications, 2003, 51(2): 175-185.
[6] ANANTHARAM V E Y. Iterative decoder architectures. IEEE Communications Magazine, 2003, 41(8): 132-140.
[7] KWON T-W, CHOI J-R. Implementation of a two-step SOVA decoder with a fixed scaling factor. IEICE Transactions on Communications, E86-B(6): Jun. 2003, 1893-1900.
[8] CHEN Y, PARHI K K. On the performance and imple- mentation issues of interleaved single parity check turbo product codes. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2005, 39(1): 35-47.