ABSTRACT We propose an input protection scheme composed of thyristor devices only without using a clamp NMOS device in order to minimize the area consumed by a pad structure in CMOS RF ICs. For this purpose, we suggest low-voltage triggering thyristor protection device structures assuming usage of standard CMOS processes, and attempt an in-depth comparison study with a conventional thyristor protection scheme incorporating a clamp NMOS device. The comparison study mainly focuses on robustness against the HBM ESD in terms of peak voltages applied to gate oxides in an input buffer and lattice heating inside protection devices based on DC and mixed-mode transient analyses utilizing a 2-dimensional device simulator. We constructed an equivalent circuit for the input HBM test environment of the CMOS chip equipped with the input ESD protection devices. And by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can occur in real HBM tests. We figure out strength of the proposed thyristor-only protection scheme, and suggest guidelines relating the design of the protection devices and circuits.
Cite this paper
nullJ. Choi and C. Park, "A Thyristor-Only Input ESD Protection Scheme for CMOS RF ICs," Circuits and Systems, Vol. 2 No. 3, 2011, pp. 170-182. doi: 10.4236/cs.2011.23025.
 P. Leroux and M. Steyaert, “High-Performance 5.2 GHz LNA with on-Chip Inductor to Provide ESD Protection,” Electronics Letters, Vol. 37, No. 7, 2001, pp. 467-469. doi:10.1049/el:20010271
 A. Chatterjee and T. Polgreen, “A Low-Voltage Triggering SCR for on-Chip ESD Protection at Output and Input Pads,” IEEE Electron Devices Letters, Vol. 12, No. 1, 1991, pp. 21-22. doi:10.1109/55.75685
 E. R. Worley, R. Gupta, B. Jones, R. Kjar, C. Nguyen and M. Tennyson, “Sub-micron Chip ESD Protection Schemes Which Avoid Avalanching Junctions,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings, Phoenix, 12 September 1995, pp. 13-20.
 J. Y. Choi, “A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices,” Communications and Network, Vol. 2, No. 1, 2010, pp. 11-25. doi:10.4236/cn.2010.21002
 H. Feng, G. Chen, R. Zhan, Q. Wu, X. Guan, H. Xie and A. Z. H. Wang, “A Mixed-Mode ESD Protection Circuit Simulation-Design Methodology,” IEEE Journal of Soilid-State Circuits, Vol. 38, No. 6, June 2003, pp. 995-1006. doi:10.1109/JSSC.2003.811978
 B. Fankhauser and B. Deutschmann, “Using Device Simulations to Optimize ESD Protection Circuits,” International Symposium on Electromagnetic Compatibility, Santa Clara, 9-13 August 2004, pp. 963-968.
 Silvaco International, “ATLAS II Framework,” Version 5.10.2.R, Silvaco International, Austin, 2005.
 J.-Y. Choi, W. S. Yang, D. Kim and Y. Kim, “Thyristor Input-Protection Device Suitable for CMOS RF ICs,” Analog Integrated Circuits and Signal Processing, Vol. 43, No. 1, April 2005, pp. 5-14. doi:10.1007/s10470-005-6566-y
 H. Feng, K. Gong and A. Wang, “A Comparison Study of ESD Protection for RFIC’s: Performance vs. Parasitic,” 2000 IEEE Radio Frequency Integrated Circuits Symposium, Boston, 11-13 June 2000, pp. 143-146.
 M.-D. Ker, C.-Y. Wu and H.-H. Chang, “Complementary-LVTSCR ESD Protection Circuit for Submicron CMOS VLSI/ULSI,” IEEE Transactions on Electron Devices, Vol. 43, No. 4, 1996, pp. 588-598. doi:10.1109/TED.1996.1210725
 Z. H. Liu, E. Rosenbaum, P. K. Ko, C. Hu, Y. C. Cheng, C. G. Sodini, B. J. Gross and T. P. Ma, “A Comparative Study of the Effect of Dynamic Stressing on High-Field Endurance and Stability of Reoxidized-Nitrided, Fluorinated and Conventional Oxides,” International Electron Devices Meeting, Washington, 8-11 February1991, pp. 723-726.
 G. Chen, H. Fang and A. Wang, “A Systematic Study of ESD Protection Structures for RF ICs,” 2003 IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, 8-10 June 2003, Vol. 46, pp. 347-350.