Cite this paper
nullA. Malkov, D. Vasiounin and O. Semenov, "A Review of PVT Compensation Circuits for Advanced CMOS Technologies," Circuits and Systems
, Vol. 2 No. 3, 2011, pp. 162-169. doi: 10.4236/cs.2011.23024
 ATA/ATA-6 Specification, 2001. http://www.t13.org/Documents/UploadedDocuments/project/d1410r3b-ATA-ATAPI-6.pdf
 S.-W. Choi and H.-J. Park, “A PVT-Insensitive CMOS Output Driver with Constant Slew Rate,” IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Tainan, Taiwan, 4-5 August 2004, pp. 116-119.
 H. Chi, D. Stout and J. Chickanosky, “Process, Voltage and Temperature Compensation of Off-Chip-Driver Circuits for Sub-0.25-pm CMOS Technology,” 10th Annual IEEE International ASIC Conference and Exhibit, Portland, 7-10 September 1997, pp. 279-282. doi:10.1109/ASIC.1997.617021
 H.-S. Jeon, D.-H. You and I.-C. Park, “Fast Frequency Acquisition All-Digital PLL Using PVT Calibration,” IEEE International Symposium on Circuits and Systems, Seattle, 18-21 May 2008, pp. 2625-2628.
 Y. Tsugita, K. Ueno, T. Hirose, T. Asai and Y. Amemiya, “On-Chip PVT Compensation Techniques for Low-Voltage CMOS Digital LSIs,” IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, 24-27 May 2009, pp. 1565-1568.
 S. Dabral and T. Maloney, “Basic ESD and I/O Design,” John Wiley & Sons Inc., New York, 1998.
 T. Takahashi, M. Uchida and T. Takashi, “A CMOS Gate Array with 600 Mb/s Simultaneous Bidirectional I/O Circuit,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 12, 1995, pp. 1544-1546. doi:10.1109/4.482204
 K. Kase and D. T. Tran, “Performance Variation Com-pensating Circuit and Method,” US Patent No.: US7,508, 246B2, 24 March 2009.
 S.-W. Choi and H.-J. Park, “A PVT-Insensitive CMOS Output Driver with Constant Slew Rate,” IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Fukuoka, 4-5 August 2004, pp. 116-119. doi:10.1109/APASIC.2004.1349423