Adaptation of the Two Sources of Code and One-Hot Encoding Method for Designing a Model of Microprogram Control Unit with Output Identification

Larysa  Titarenko; Alexander  Barkalov; Łukasz  Smoliński

doi:10.4236/ica.2015.62012

Łukasz Smoliński^*, Alexander Barkalov, Larysa Titarenko

Abstract: This article presents a proposal for a model of a microprogram control unit (CMCU) with output identification adapted for implementation in complex programmable logic devices (CPLD) equipped with integrated memory modules [1]. An approach which applies two sources of code and one-hot encoding has been used in a base CMCU model with output identification [2] [3]. The article depicts a complete example of processing for the proposed CMCU model. Furthermore, it also discusses the advantages and disadvantages of the approach in question and presents the results of the experiments conducted on a real CPLD system.

Keywords: CPLD, PAL, UFM, CLB, Two Sources of Code, One-Hot Encoding, CMCU

Cite this paper: Smoliński, Ł. , Barkalov, A. and Titarenko, L. (2015) Adaptation of the Two Sources of Code and One-Hot Encoding Method for Designing a Model of Microprogram Control Unit with Output Identification. Intelligent Control and Automation, 6, 116-125. doi: 10.4236/ica.2015.62012.

References

[1] Wisniewski, R. (2009) Synthesis of Compositional Microprogram Control Units for Programmable Devices. University of Zielona Gora Press, Poland.

[2] Barkalov, A., Titarenko, L. and Smoliński, L. (2014) CMCU Model with Base Structure Dedicated for CPLD Systems. Przeglqd Elektroniczny, 12, 25-29.

[3] Barkalov, A., Titarenko, L. and Smoliński, L. (2012) Optimization of Control Unit Based on Construction of CPLD, Pomiary, Automatyka, Kontrola, 58, 93-96.

[4] Monmasson, E., Idkhajine, L., Cirstea, M., Bahri, I., Tisan, A. and Naouar, M. (2011) FPGAs in Industrial Control Applications. IEEE Transactions on Industrial Informatics, 7, 224-242.
http://dx.doi.org/10.1109/TII.2011.2123908

[5] Kania, D. (2004) The Logic Synthesis for the PAL-Based Complex Programmable Logic Devices. Zeszyty Naukowe, Elektronika, 14, 5-212.

[6] Kubica D. and Kania D. (2011) Synteza logiczna zespolu funkcji ukierunkowana na minimalizacje liczby wykorzystywanych bloków logicznych PAL w oparciu o zmodyfikowany graf wyjsc. Pomiary, Automatyka, Kontrola, 57, 737-740.

[7] Monmasson, E. and Cirstea, M. (2007) FPGA Design Methodology for Industrial Control Systems—A Review. IEEE Transactions on Industrial Informatics, 54, 1824-1842.
http://dx.doi.org/10.1109/TIE.2007.898281

[8] Garcia-Vargas, I., Senhadji-Navarro, R., Jimenez-Moreno, G., Civit-Balcells, A. and Guerra-Gutierrez, P. (2007) ROM-Based Finite State Machine Implementation in Low Cost FPGAs. IEEE International Symposium on Industrial Electronics, Vigo, 4-7 June 2007, 2342-2347.
http://dx.doi.org/10.1109/ISIE.2007.4374972

[9] Rafla, N. and Davis, B. (2006) A Study of Finite State Machine Coding Styles for Implementation in FPGA. 49th IEEE International Midwest Symposium on Circuits and Systems, Puerto Rico, 6-9 August 2006, 337-341.

[10] Czerwiński, R. and Kania, D. (2009) Synthesis of Finite State Machines for CPLDs. International Journal of Applied Mathematics and Computer Science, 19, 647-659.
http://dx.doi.org/10.2478/v10006-009-0052-0

[11] Anand, B.P. and Saravanan, C.G. (2012) Development of Research Engine Control Unit Using FPGA-Based Embedded Control System. Journal of KONES Powertrain and Transport, 19, 9-18.

[12] Salauyou, V. and Grzes, T. (2007) FSM State Assignment Methods for Low-Power Design. 6th International Conference on Computer Information Systems and Industrial Management Applications, 2007, CISIM ’07, Minneapolis, 28-30 June 2007, 345-350.

[13] Czerwinski, R. and Kania, D. (2012) Area and Speed Oriented Synthesis of FSMs for PAL-Based CPLDs. Microprocessors and Microsystems, 36, 45-61.
http://dx.doi.org/10.1016/j.micpro.2011.06.004

[14] Barkalov, A. and Titarenko, L. (2008) Logic Synthesis for Compositional Microprogram Control Units. Springer, Berlin.

[15] Altera (2007) Using the UFM in MAX II Devices. www.altera.com/literature/an/an489.pdf

[16] Cypress (2003) Delta39K ISR CPLD Family.
http://pdf.datasheetcatalog.com/datasheet2/9/0pfaeyx4ushkk0zzjksaycgxhqky.pdf

[17] Baranov, S. (2008) Logic and System Design of Digital Systems. TUT Press, Tallin.

[18] Maxfield, C. (2004) The Design Warrior’s Guide to FPGAs: Devices, Tools and Flows. Elsevier, Amsterdam.

[19] Barkalov, A., Titarenko, L. and Smoliński, L. (2013) Hardware Reduction for Compositional Microprogram Control Unit Dedicated for CPLD Systems. Proceedings of IEEE East-West Design and Test Symposium-EWDTS 2013, Rostov-on-Don, 27-30 September 2013, 1-6.
http://dx.doi.org/10.1109/EWDTS.2013.6673200

[20] Barkalov, A., Titarenko, L. and Smoliński, L. (2014) The Application and Adaptation of the Two Sources of Code and Natural Encoding Method for Designing a Model of Microprogram Control unit with Base Structure. Circuits and Systems, 5, 301-308.
http://dx.doi.org/10.4236/cs.2014.512031

[21] Barkalov, A., Titarenko, L. and Smoliński, L. (2011) Optimization of Microprogram Control Unit with Code Sharing. Proceedings of IEEE East-West Design & Test Symposium-EWDTS 2011, Sevastopol, 9-12 September 2011, 55-59.
http://dx.doi.org/10.1109/EWDTS.2011.6116573