CS  Vol.6 No.3 , March 2015
Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers
ABSTRACT
The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.

Cite this paper
Jaiswal, N. and Gamad, R. (2015) Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers. Circuits and Systems, 6, 81-92. doi: 10.4236/cs.2015.63009.
References
[1]   Alser, M.H. and Assaad, M.M. (2011) Design and Modeling of Low-Power Clockless Serial Link for Data Communication Systems. National Postgraduate Conference, Kuala Lumpur, 19-20 September 2011, 1-5.
http://dx.doi.org/10.1109/NatPC.2011.6136441

[2]   Geurts, T., Rens, W., Crols, J., Kashiwakura, S. and Segawa, Y. (2004) A 2.5 Gbps - 3.125 Gbps Multi-Core Serial-Link Transceiver in 0.13 μm CMOS. Proceeding of the 30th European Solid-State Circuits Conference, 21-23 September 2004, 487-490.
http://dx.doi.org/10.1109/ESSCIR.2004.1356725

[3]   Park, J.Y., Kang, J., Park, S. and Flynn, M.P. (2009) A 9 Gbit/s Serial Transceiver for On-Chip Global Signaling over Lossy Transmission Lines. IEEE Transactions on Circuits and Systems (TCAS), 56, 1807-1817.
http://dx.doi.org/10.1109/TCSI.2009.2027634

[4]   Philpott, R.A., Humble, J.S., Kertis, R.A., Fritz, K.E., Gilbert, B.K. and Daniel, E.S. (2008) A 20Gb/s SerDes Transmitter with Adjustable Source Impedance and 4-Tap Feed-Forward Equalization in 65 nm Bulk CMOS. IEEE Custom Integrated Circuits Conference (CICC), San Jose, 21-24 September 2008, 623-626.

[5]   Chen, D.Y. (2007) SerDes Transceivers for High Speed Serial Communications. Department of Electronics, Carleton University, Ottawa.

[6]   Bhatti, R.Z., Denneau, M. and Draper, J. (2006) 2 Gbps SerDes Design Based on IBM Cu-11 (130 nm) Standard Cell Technology. 16th ACM Great Lakes Symposium on VLSI, 198-203.

[7]   Ghoneima, M., Ismail, Y., Khellah, M., Tschanz, J. and De, V. (2009) Serial Link Bus: A Low-Power On-Chip Bus Architecture. IEEE Transactions on Circuits and Systems I (TCAS), 2020-2032.

[8]   Safwat, S., Hussein, E.E., Ghoneima, M. and Ismail, Y. (2011) A 12 Gbps All Digital Low Power SerDes Transceiver for On-Chip Networking. 2011 IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, 15-18 May 2011, 1419-1422.
http://dx.doi.org/10.1109/ISCAS.2011.5937839

[9]   Hussein, E.E., Safwat, S., Ghoneima, M. and Ismail, Y. (2012) A 16 Gbps Low Power Self Timed SerDes Transceiver for Multi-Core Communication. 2012 IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, 20-23 May 2012, 1660-1663.
http://dx.doi.org/10.1109/ISCAS.2012.6271576

[10]   Tadros, R.N., Elsayed, A.H., Ghoneima, M. and Ismail, Y. (2014) A Variation Tolerant Driving Techniques for All-Digital Self-Timed 3-Level Signaling High-Speed SerDes Transceiver for On-Chip Networks. 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, 1-5 June 2014, 1520-1523.
http://dx.doi.org/10.1109/ISCAS.2014.6865436

[11]   Elsayed, A.H., Tadros, R.N., Ghoneima, M. and Ismail, Y. (2014) Low Power All-Digital Manchester Encoding Based High-Speed SerDes Transceiver for On-Chip Networks. 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, 1-5 June 2014, 2752-2755.
http://dx.doi.org/10.1109/ISCAS.2014.6865743

[12]   Suzuki, Y., Odagawa, K. and Abe, T. (1973) Clocked CMOS Calculator Circuitry. IEEE Journal of Solid State Circuits, 8, 462-469.
http://dx.doi.org/10.1109/JSSC.1973.1050440

 
 
Top