CS  Vol.6 No.1 , January 2015
A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop
ABSTRACT
Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.

Cite this paper
Wang, X. and Kwasniewski, T. (2015) A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop. Circuits and Systems, 6, 13-19. doi: 10.4236/cs.2015.61002.
References
[1]   Farjad-Rad, R., Dally, W., Ng, H.-T., Senthinathan, R., Lee, M.-J.E., Rathi, R. and Poulton, J. (2002) A Low-Power Multiplying DLL for Low-Jitter Multigigaherz Clock Generation. IEEE Journal of Solid State Circuit, 37, 1804-1811.
http://dx.doi.org/10.1109/JSSC.2002.804340

[2]   Liu, C.-Y. and Chen, W.-Z. (2011) Spur Suppression Technique for Multiplied Delay Locked Loop. Proceedings of IEEE International Symposium on Radio Frequency Integration Technology (RFIT), 153-156.

[3]   Du, Q.J., Zhuang, J.C. and Kwasniewski, T. (2006) A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier with Period Error Compensation for Spur Reduction. IEEE Transactions on Circuits Systems II, 53, 1205-1209.
http://dx.doi.org/10.1109/TCSII.2006.883103

[4]   Elshazly, A., Inti, R., Young, B. and Hanumolu, P.K. (2013) Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops. IEEE Journal of Solid-State Circuits, 48, 1416-1428.
http://dx.doi.org/10.1109/JSSC.2013.2254552

[5]   Helal, B.M.M., Straayer, Z., Wei, G.-Y. and Perrott, M.H. (2008) A Highly Digital MDLL-Based Frequency Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance. IEEE Journal of Solid-State Circuits, 43, 855-863.
http://dx.doi.org/10.1109/JSSC.2008.917372

[6]   Ali, T.A., Hafez, A.A., Drost, R., Ho, R. and Yang, C.-K.K. (2011) A 4.6 GHz MDLL with -46 dBc Reference Spur and Aperture Position Tuning. ISSCC, Dig. Tech. Papers, 466-468.

[7]   Marzin, G., Levantino, S., Samori, C. and Lacaita, A.L. (2014) A 1.7 GHz MDLL-Based Fractional-N Frequency Synthesizer with 1.4 ps RMS Integrated Jitter and 3 mW Power Using a 1b TDC. ISSCC, Dig. Tech. Papers, 360-362.

[8]   Rhee, W. (1999) Design of High Performance CMOS Charge Pumps in Phase Locked Loop. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 1, 545-548.

[9]   Fischette, D. (2009) First Time, Every Time Practical Tips for Phase Locked Loop Design.
http://www.delroy.com/PLL_dir/tutorial/PLL_tutorial_slides.pdf

[10]   Shu, K. and Sanchez-Sinencio, E. (2005) CMOS PLL Synthesizers: Analysis and Design. Springer, Berlin.

 
 
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