JIS  Vol.5 No.3 , July 2014
Parallelized Hashing via j-Lanes and j-Pointers Tree Modes, with Applications to SHA-256
Author(s) Shay Gueron
ABSTRACT

j-lanes tree hashing is a tree mode that splits an input message into j slices, computes j independent digests of each slice, and outputs the hash value of their concatenation. j-pointers tree hashing is a similar tree mode that receives, as input, j pointers to j messages (or slices of a single message), computes their digests and outputs the hash value of their concatenation. Such modes expose parallelization opportunities in a hashing process that is otherwise serial by nature. As a result, they have a performance advantage on modern processor architectures. This paper provides precise specifications for these hashing modes, proposes appropriate IVs, and demonstrates their performance on the latest processors. Our hope is that it would be useful for standardization of these modes.


Cite this paper
Gueron, S. (2014) Parallelized Hashing via j-Lanes and j-Pointers Tree Modes, with Applications to SHA-256. Journal of Information Security, 5, 91-113. doi: 10.4236/jis.2014.53010.
References
[1]   Gueron, S. (2013) A j-Lanes Tree Hashing Mode and j-Lanes SHA-256. Journal of Information Security, 4, 7-11.

[2]   FIPS (2012) Secure Hash Standard (SHS), Federal Information Processing Standards Publication 180-4. http://csrc.nist.gov/publications/fips/fips180-4/fips-180-4.pdf

[3]   Intel (2013) Intel® Architecture Instruction Set Extensions Programming Reference.
http://software.intel.com/en-us/file/319433-017pdf

[4]   ARM (2013) Neon, ARM. http://www.arm.com/products/processors/technologies/neon.php

[5]   Reinders, J. (2013) AVX-512 Instructions, Intel Developer Zone.
http://software.intel.com/en-us/blogs/2013/avx-512-instructions

 
 
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