A major concern in
modern smart-phones and hand-held devices is a way of mitigating the time
interval error (TIE) perceived at high-speed digital transits along the traces
of the circuit-board (rigid and or flexible) used in baseband infrastructures.
Indicated here is a way of adopting a planar fractal inductor configuration to
improvise the necessary time-delay in the transits of digital signal phase
jitter and reduce the TIE. This paper addresses systematic design
considerations on fractal inductor geometry commensurate with practical aspects
of its implementation as delaylines in the high-speed digital transports at
the baseband operations of smart-phone infrastructures. Experimental results
obtained from a test module are presented to illustrate the efficacy of the design and acceptable delay
performance of the test structure commensurate with the digital transports of
Cite this paper
Neelakanta, P. and Noori, A. (2014) Mitigating Time Interval Error (TIE) in High-Speed Baseband Digital Transports: Design for Delay Compensation at Baseband Infrastructure of Smart-Phones Using Fractal Dispersive Delay-Lines. Circuits and Systems
, 115-123. doi: 10.4236/cs.2014.55013
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