CS  Vol.5 No.5 , May 2014
Mitigating Time Interval Error (TIE) in High-Speed Baseband Digital Transports: Design for Delay Compensation at Baseband Infrastructure of Smart-Phones Using Fractal Dispersive Delay-Lines
ABSTRACT

A major concern in modern smart-phones and hand-held devices is a way of mitigating the time interval error (TIE) perceived at high-speed digital transits along the traces of the circuit-board (rigid and or flexible) used in baseband infrastructures. Indicated here is a way of adopting a planar fractal inductor configuration to improvise the necessary time-delay in the transits of digital signal phase jitter and reduce the TIE. This paper addresses systematic design considerations on fractal inductor geometry commensurate with practical aspects of its implementation as delaylines in the high-speed digital transports at the baseband operations of smart-phone infrastructures. Experimental results obtained from a test module are presented to illustrate the efficacy of the design and acceptable delay performance of the test structure commensurate with the digital transports of interest.


Cite this paper
Neelakanta, P. and Noori, A. (2014) Mitigating Time Interval Error (TIE) in High-Speed Baseband Digital Transports: Design for Delay Compensation at Baseband Infrastructure of Smart-Phones Using Fractal Dispersive Delay-Lines. Circuits and Systems, 5, 115-123. doi: 10.4236/cs.2014.55013.
References
[1]   Oh, K.S. and Yuan, X. (2012) High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting. Pearson Education, Inc., Boston.

[2]   Bosshart, W.C. (1984) Printed Circuit Boards—Design and Technology. Tata-McGraw-Hill Publishing Co., New Delhi.

[3]   Maric, A., Radosavljevic, G., Zivanov, M. and Zivanov, L. (2008) Modeling and Characterization of Fractal Based RF Inductors on Silicon Substrate. Proceedings of the 7th International Conference on Advanced Semiconductor Devices and Microsystems, Smolenice Castle, 12-16 October, 191-194.

[4]   Kabiri, A., Bait-Suwailam, M., Kermani, M.H. and Ramahi, O.M. (2009) The Effect of Loss-Tangent on Laddering Behavior in Delay Lines. Progress in Electromagnetic Research Letters, 12, 161-170.
http://dx.doi.org/10.2528/PIERL09102503

[5]   Cohen, N. (2005) Fractals’ New Era in Military Antenna Design. RF Design, 12-17.

[6]   Jahanbakht, M. and Neyestanak, A.A.L. (2011) Coplanar MEMS Phased Array Antenna Using Koch Fractal Geometry. Progress in Electromagnetics Research M, 17, 29-42.
http://dx.doi.org/10.2528/PIERM11010301

[7]   Ogorzalek, M.J. (2013) Fractal Capacitors.
http://www.eie.polyu.edu.hk/~maciej/pdf/Fractal_capacitors.pdf

[8]   Baliarda, C.P., Romeu, J. and Cardama, A. (2000) The Koch Monopole: A Small Fractal Antenna. IEEE Transactions on Antennas and Propagation, 48, 1773-1781.
http://dx.doi.org/10.1109/8.900236

[9]   (2013) Fractal Miniaturization in RF and Microwave Networks.
http://www.fractal.org/Fractal-Research-and-Products/Fractal-waves.pdf

[10]   Kumar, P., Sharma, M.L., Chawla, P., Khanna, R. and Arora, D. (2011) Introduction of Multiband Fractal Antenna and RF MEMS Switches and Reconfigurable RF Front End Section of Mobile. International Journal of Communication Engineering Applications, 2, 243-248.

[11]   Abuzeid, O.M., Al-Rabadi, A.N. and Alkhaldi, H.S. (2010) Fractal Geometry-Based Hypergeometric Time Series Solution to the Hereditary Thermal Creep Model for the Contact of Rough Surfaces Using the Kelvin-Voigt Medium. Mathematical Problems in Engineering, 2010, Article ID: 652306.
http://dx.doi.org/10.1155/2010/652306

[12]   Blazek, V., Neelakantaswamy, P.S. and Reddy, V.C.V.P. (1975) Generation of Complex Waveforms for Biomedical Applications. IEEE Transactions on Biomedical Engineering, BME-22, 535-536.
http://dx.doi.org/10.1109/TBME.1975.324478

[13]   Neelakanta, P.S. and Preechayasomboon, A. (1999) Mitigating EMI in High-Speed Digital Transmission Networks: Part I. Compliance Engineering, 16, 36-47.

[14]   Neelakanta, P.S. and Sivaraks, J. (2000) Mitigating EMI in High-Speed Digital Transmission Networks: Part II. Com pliance Engineering, 17, 34-47.

[15]   Hizon, J.R.E., et al. (2007) A Study of Layout Strategies in RF CMOS Design. Proceedings of the Progress in Electromagnetics Research Symposium, Prague, 27-30 August, 497-502.

[16]   Burghartz, J.N., Ruehli, A.E., Jenkins, K.A., Soyuer, M. and Nguyen-Ngoc, D. (1997) Novel Substrate Contact Structure for High Q Silicon Integrated Spiral Inductors. Technical Digest International Electron Devices Meeting, Washington DC, 10 December, 55-58.

[17]   Soyuer, M., Burghartz, M., Jenkins, J.N., Ponnampalli, K.A., Ewen, J.R. and Pence, W.E. (1995) Multi-Level Monolithic Inductors in Silicon Technology. Electronics Letters, 31, 359-360.
http://dx.doi.org/10.1049/el:19950241

[18]   Rosales, M.D., Hizon, J.R.E., Alarcon, L.P. and Sabido, D.J. (2005) Monolithic Spiral Inductors for a 0.25 um Digital CMOS Process. Proceedings of IEEE Region 10 Conference, Melbourne, 21-24 November, 1-6.

 
 
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