CS  Vol.5 No.4 , April 2014
Experimental Demonstration of gm/ID Based Noise Analysis

Recent studies using BSIM3 models have suggested that noise depends on the transconductance-to-drain ratio gm/ID of a transistor. However, to the best of our knowledge, no experimental result demonstrating gm/ID dependent noise previously observed in simulation is available in the literature. This paper examines the underlying principles that make it possible to analyze noise using gm/ID based noise analysis. Qualitative discussion of normalized noise is presented along with experimental results from a 130 nm CMOS process. A close examination of the experimental results reveals that the device noise is width independent from 1 Hz to 10 kHz. Moreover, noise increases as gm/ID is reduced. The experiment observation that noise is width independent makes it possible for circuit designers to generate normalized parameters that are used to study noise intuitively and accurately.

Cite this paper
Ou, J. , Ferreira, P. and Lee, J. (2014) Experimental Demonstration of gm/ID Based Noise Analysis. Circuits and Systems, 5, 69-75. doi: 10.4236/cs.2014.54009.
[1]   Gray, P., Hurst, P., Lewis, S. and Meyer, R. (2000) Analysis and Design of Analog Integrated Circuits. John Wiley and Sons, New York.

[2]   Silveira, F., Flandre, D. and Jespers, P.G.A. (1996) A gm/ID Based Methodology for the Design of CMOS Analog Circuits and Its Application to the Synthesis of a Silicon-on-Insulator Micropower OTA. IEEE Journal of Solid-State Circuits, 31, 1314-1319. http://dx.doi.org/10.1109/4.535416

[3]   Barabino, N., Fiorelli, R. and Silveira, F. (2010) Efficiency Based Design Flow for Fully-Integrated Class C RF Power Amplifiers in Nanometric CMOS. Proceedings of IEEE ISCAS, 2010, 2223-2226.

[4]   Fiorelli, R., Peralías, E.J. and Silveira, F. (2011) LC-VCO Design Optimization Methodology Based on the gm/ID Ratio for Nanometer CMOS Technologies. IEEE Transactions on Microwave Theory and Techniques, 59, 1822-1831.

[5]   Ou, J. and Farahmand, F. (2012) Transconductance/Drain Current Based Distortion Analysis for Analog CMOS Integrated Circuits. IEEE Proceedings of NEWCAS, June 2012, 61-64.

[6]   Ou, J. and Ferreira, P.M. (2013) Transconductance/Drain Current Based Sensitivity Analysis for Analog CMOS Integrated Circuits. IEEE Proceedings of NEWCAS, June 2013.

[7]   Abdelfattah, O., Shih, I. and Roberts, G. (2013) A Simple Analog CMOS Design Tool Using Transistor Dimension-Independent Parameters. Proceedings of IEEE ISCAS, Beijing, May 2013.

[8]   Jespers, P. (2010) The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits. Springer, Louvain-la-Neuve, Belgium.

[9]   Ou, J. (2011) gm/ID Based Noise Analysis for CMOS Analog. IEEE Proceedings of MWSCAS, Seoul, August 2011, 26-29.

[10]   Alvarez, E. and Abusleme, A. (2012) Noise Power Normalisation: Extension of gm/ID Technique for Noise Analysis. Electronics Letters, 48, 430. http://dx.doi.org/10.1049/el.2011.3730

[11]   Alvarez, E., Avila, D., Campillo, H., Dragone, A. and Abusleme, A. (2012) Noise in Charge Amplifiers—A gm/ID Approach. IEEE Transactions on Nuclear Science, 59, 2012.

[12]   Rhayem, J., Gillon, R., Tack, M., Valenza, M. and Hoffmann, A. (2002) Comments on Existing 1/f Noise Models: SPICE, HSPICE and BSIM3v3 for MOSFETs in Circuit Simulators. European Solid-State Device Research Conference, Firenze, September 2002.

[13]   Tsividis, Y. (1999) Operation and Modeling of the MOS Transistor. McGraw-Hill, New York.

[14]   Dronavalli, S. and Jindal, R.P. (2006) CMOS Device Noise Considerations for Terabit Lightwave Systems. IEEE Transactions on Electron Devices, 53, 623-630.

[15]   Tiemeijer, L.F., Havens, R.J., Kort, R.D. and Scholten, A.J. (2005) Improved Y-Factor Method for Wide-Band OnWafer Noise-Parameter Measurements. IEEE Transactions on Microwave Theory and Techniques, 53, 2917-2925.