A domain extension algorithm to correct the comparator
offsets of pipeline analog-to-digital converters (ADCs) is presented, in which
the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-domain.
This algorithm is designed for high speed and low comparator accuracy
application. The comparator offset correction ability is improved. This new
approach also promises significant improvements to the spurious-free
dynamic range (SFDR), the total harmonic distortion (THD), the signal-to-noise
ratio (SNR) and the minor analog and digital circuit modifications. Behavioral
simulation results are presented to demonstrate the effectiveness of the
algorithm, in which all absolute values of comparator offsets are set to |3Vref/8|. SFDR, THD and SNR are improved, from 34.62-dB, 34.63-dB and
30.33-dB to 60.23-dB, 61.14-dB and 59.35-dB, respectively, for
a 10-bit pipeline ADC.
Cite this paper
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