A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.
 M. Yoshika, K. Ishikawa, T. Takayama and S. Tsukamoto, “A 10-b 50-MS/s 820-μW SAR ADC with On-Chip Digital Calibration,” IEEE Transactions on Biomedical Circuits and Systems, Vol. 4, No. 6, 2010, pp. 410-416. http://dx.doi.org/10.1109/TBCAS.2010.2081362
 C. C. Liu, S. J. Chang, G. Y. Huang, Y. Z. Lin, C. M. Huang, C. H. Huang, L. Bu and C. C. Tsai, “A 10b 100MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation,” IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, 7-11 Febraury 2010, pp. 386-387.
 S. H. Cho, C. K. Lee, J. K. Kwon and S. T. Ryu, “A 550-μW 10-b 40-MS/s SAR ADC with Multistep Addition-Only Digital Error Correction,” IEEE Journal of Solid-State Circuits, Vol. 46, No. 8, 2011, pp. 1881-1892. http://dx.doi.org/10.1109/JSSC.2011.2151450
 Y. Zhu, C.-H. Chan, U-F. Chio, S.-W. Sin, S.-P. U, R. P. Martins and F. Maloberti, “A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 45, No. 4, 2010, pp. 1111-1121. http://dx.doi.org/10.1109/JSSC.2010.2048498
 Y.-K. Cho, Y.-D. Jeon, J.-W. Nam and J.-K. Kwon, “A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter with a Capacitor Reduction Technique,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 57, No. 7, 2010, pp. 502-506.
 P. J. A. Harpe, C. Zhou, Y. Bi, N. P. van der Meijs, X. Wang, K. Philips, G. Dolmans and H. de Groot, “A 26 μW 8 bit 10MS/s Asynchronous SAR ADC for Low Energy Radios,” IEEE Journal of Solid-State Circuits, Vol. 46, No. 7, 2011, pp. 1585-1595. http://dx.doi.org/10.1109/JSSC.2011.2143870
 A. Shikata, R. Sekimoto, T. Kuroda and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC with Tri-Level Comparator in 40nm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 47, No. 4, 2012, pp. 1022-1030. http://dx.doi.org/10.1109/JSSC.2012.2185352
 J. McNeill, K. Chan, M. Coln, C. David and C. Brenneman, “All-Digital Background Calibration of a Successive Approximation ADC Using the ‘Split ADC’ Architecture,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 58, No. 10, 2011, pp. 2355-2365.
 W. Liu, P. Huang and Y. Chiu, “A 12-bit, 45-MS/s, 3- mW Redundant SAR ADC with Digital Calibration,” IEEE Journal of Solid-State Circuits, Vol. 46, No. 11, 2011, pp. 2661-2672. http://dx.doi.org/10.1109/JSSC.2011.2163556
 R. Xu, B. Liu and J. Yuan, “Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array with Dithering,” IEEE Journal of Solid-State Circuits, Vol. 47, No. 9, 2011, pp. 2129-2140. http://dx.doi.org/10.1109/JSSC.2012.2198350
 J. H. Cheong, K. L. Chan, P. B. Khannur, K. T. Tiew, and M. Je, “A 400-nW 19.5-fJ/Conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18-μm CMOS,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 58, No. 7, 2011, pp. 502-506.