Logical Function Decomposition Method for Synthesis of Digital Logical System Implemented with Programmable Logic Devices (PLD)

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References

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[2] C. H. Roth, “Fundamentals of Logic Design,” West Publishing Company, Eagan, 1999, pp. 148-172.

[3] Al. Valachi, Fl. Hoza, V. Onofrei and R. Silion, “Analiza, Sinteza si Testarea Dispozitivelor Numerice,” Nord-Est, 1993, pp. 31-32; 45-53.

[4] J. A. Brzozowski and T. Luba, “Decomposition of Boolean Functions Specified by Cubes,” Journal of Multiple-Valued Logic and Soft Computing, Vol. 9, 2003.

[5] M. Rawski, “Decomposition of Boolean Function Sets,” Electronics and Telecommunications Quarterly, Vol. 53, No. 3, 2007, pp. 231-249.

[6] J. A. Brzozowski and T. Luba, “Logic Decomposition Aimed at Programmable Cell Arrays,” International Conference of Microelectronics: Microelectronics, Vol. 1783, 1992, pp. 77-88. http://dx.doi.org/10.1117/12.130993

[7] S. J. E. Wilton, “SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays,” FPGA, 1998, pp. 171-178.

[8] “Logic Synthesis Strategy for FPGAs with Embedded Memory Blocks,” Mariusz Rawski, Grzegorz Borowik, Tadeusz Luba, Pawel Tomaszewicz, Bogdan j. Falkowski. Przeglad Elektrotechnic Znyelectrical Review), R. 86 NR 11a/2010.