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 CS  Vol.4 No.7 , November 2013
Two Analytical Methods for Detection and Elimination of the Static Hazard in Combinational Logic Circuits
Abstract: In this paper, the authors continue the researches described in [1], that consists in a comparative study of two methods to eliminate the static hazard from logical functions, by using the form of Product of Sums (POS), static hazard “0”. In the first method, it used the consensus theorem to determine the cover term that is equal with the product of the two residual implicants, and in the second method it resolved a Boolean equation system. The authors observed that in the second method the digital hazard can be earlier detected. If the Boolean equation system is incompatible (doesn’t have solutions), the considered logical function doesn’t have the static 1 hazard regarding the coupled variable. Using the logical computations, this method permits to determine the needed transitions to eliminate the digital hazard.
Cite this paper: M. Timis, A. Valachi, A. Barleanu and A. Stan, "Two Analytical Methods for Detection and Elimination of the Static Hazard in Combinational Logic Circuits," Circuits and Systems, Vol. 4 No. 7, 2013, pp. 466-471. doi: 10.4236/cs.2013.47061.
References

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