Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.
 R. X. Gu and M. I. Elmasry, “Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 5, 1996, pp. 707-713.
 N. S. Kim, et al., “Leakage Current: Moore’s Law Meets Static Power,” IEEE Computer, Vol. 36, No. 12, 2003, pp. 68-75. http://dx.doi.org/10.1109/MC.2003.1250885
 S. Borkar, “Design Challenges of Technology Scaling,” IEEE Micro, Vol. 19, No. 4, 1999, pp. 23-29. http://dx.doi.org/10.1109/40.782564
 S. Cristoloveanu and G. Reichert, “Recent Advances in SOI Materials and Device Technologies for High Temperature,” Proceedings of High-Temperature Electronic Materials, Devices and Sensors, San Diego, 22-27 February 1998, pp. 86-93.
 R. Yan, A. Ourmazd and K. F. Lee, “Scaling the Si MOSFET: From Bulk to SOI to Bulk,” IEEE Transactions on Electron Devices, Vol. 39, No. 7, 1992, pp. 17041710. http://dx.doi.org/10.1109/16.141237
 S. Mutoh, et al., “1-V Power Supply High—Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 8, 1995, pp. 847-854.
 M. Anis, S. Areibi and M. Elmasry, “Design and Optimization of Multi-Threshold CMOS (MTCMOS) Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 10, 2003, pp. 1324-1342. http://dx.doi.org/10.1109/TCAD.2003.818127
 H. Kawaguchi, K. Nose and T. Sakurai, “A Super Cutoff CMOS (SCCMOS) Scheme for 0.5 V Supply Voltage with Picoampere Standby Current,” IEEE Journal of SolidState Circuits, Vol. 35, No. 10, 2000, pp. 1498-1501. http://dx.doi.org/10.1109/4.871328
 S. J. Abou-Samra and A. Guyot, “Performance/Complexity Space Exploration: Bulk vs. SOI,” Proceedings of the International Workshop on Power and Timing Modelling, Optimization and Simulation, Lyngby, 7-9 October 1998.
 J. P. Colinge, “Silicon-on-Insulator Technology: Materials to VLSI,” Kluwer Academic Publishers, Boston, 1997. http://dx.doi.org/10.1007/978-1-4757-2611-4
 H. Jeon, Y. B. Kim and M. Choi, “Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems,” IEEE Transactions on Instrumentation and Measurement, Vol. 59, No. 5, 2010, pp. 1127-1133. http://dx.doi.org/10.1109/TIM.2010.2044710