Accurate test effectiveness estimation for analogue and mixed-signal
Systems on a Chip (SoCs) is currently prohibitive in the design environment.
One of the factors that sky rockets fault simulation costs is the number of
structural faults which need to be simulated at circuit-level. The purpose of
this paper is to propose a novel fault list compression technique by defining a
stratified fault list, build with a set of “representative” faults,
one per stratum. Criteria to partition the fault list in strata, and to
identify representative faults are presented and discussed. A fault
representativeness metric is proposed, based on an error probability. The
proposed methodology allows different tradeoffs between fault list compression
and fault representation accuracy. These tradeoffs may be optimized for each
test preparation phase. The fault representativeness vs. fault list compression
tradeoff is evaluated with an industrial case study—a DC-DC (switched buck
converter). Although the methodology is presented in this paper using a very
simple fault model, it may be easily extended to be used with more elaborate
fault models. The proposed technique is a significant contribution to make
mixed-signal fault simulation cost-effective as part of the production test
Cite this paper
N. Guerreiro, M. Santos and P. Teixeira, "Analogue and Mixed-Signal Production Test Speed-Up by Means of Fault List Compression," Circuits and Systems
, Vol. 4 No. 5, 2013, pp. 407-421. doi: 10.4236/cs.2013.45054
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