Switchable PLL Frequency Synthesizer andHot Carrier Effects

ABSTRACT

In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 µm n-well CMOS process. Cadence/Spectre simulations show that the frequency range of the switchable phased-locked loop is between 320 MHz to 1.15 GHz. The experimental results show that the RMS jitter of the phase-locked loop changes from 26 ps to 123 ps as output frequency varies. For 700 MHz carrier frequency, the phase noise of the phase-locked loop reaches as low as ?81 dBc/Hz at 10 kHz offset frequency and ?104 dBc/Hz at 1 MHz offset frequency. A device degradation model due to hot carrier effects has been used to analyze the jitter and phase noise performance in an open loop voltage-controlled oscillator. The oscillation frequency of the voltage-controlled oscillator decreases by approximately 100 to 200 MHz versus the bias voltage and the RMS jitter increases by 40 ps under different phase-locked loop output frequencies after 4 hours of stress time.

In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 µm n-well CMOS process. Cadence/Spectre simulations show that the frequency range of the switchable phased-locked loop is between 320 MHz to 1.15 GHz. The experimental results show that the RMS jitter of the phase-locked loop changes from 26 ps to 123 ps as output frequency varies. For 700 MHz carrier frequency, the phase noise of the phase-locked loop reaches as low as ?81 dBc/Hz at 10 kHz offset frequency and ?104 dBc/Hz at 1 MHz offset frequency. A device degradation model due to hot carrier effects has been used to analyze the jitter and phase noise performance in an open loop voltage-controlled oscillator. The oscillation frequency of the voltage-controlled oscillator decreases by approximately 100 to 200 MHz versus the bias voltage and the RMS jitter increases by 40 ps under different phase-locked loop output frequencies after 4 hours of stress time.

KEYWORDS

CMOS Phase-Locked Loop, Voltage-Controlled Oscillator, Hot Carrier Effects, Jitter, Phase Noise

CMOS Phase-Locked Loop, Voltage-Controlled Oscillator, Hot Carrier Effects, Jitter, Phase Noise

Cite this paper

nullY. Liu, A. Srivastava and Y. Xu, "Switchable PLL Frequency Synthesizer andHot Carrier Effects,"*Circuits and Systems*, Vol. 2 No. 1, 2011, pp. 45-52. doi: 10.4236/cs.2011.21008.

nullY. Liu, A. Srivastava and Y. Xu, "Switchable PLL Frequency Synthesizer andHot Carrier Effects,"

References

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[9] E. Xiao and J. S. Yuan, “Hot Carrier and Soft Breakdown Effects on VCO Performance,” IEEE Transactions on Microwave Theory and Techniques, Vol. 50, No. 11, 2002, pp. 2453-2458. doi:10.1109/TMTT.2002.804632

[10] C. Zhang and A. Srivastava, “Hot Carrier Effects on Jitter and Phase Noise in CMOS Voltage-Controlled Oscilla- tors,” Proceedings of SPIE-Noise in Devices and Circuits III, Austin, 23-26 May 2005, pp. 52-62.

[11] C. Zhang and A. Srivastava, “Hot Carrier Effects on Jitter Performance in CMOS Voltage Controlled Oscillators,” Fluctuation and Noise Letters, Vol. 6, No. 3, 2006, pp. 329-334. doi:10.1142/S0219477506003446

[12] S. Pellerano, S. Laventin, C. Samori and A, Lacaita, “A 13.5-mW 5-GHz Frequency Synthesizer with Dynamic- logic Frequency Divider,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 2, 2004, pp. 378-383. doi:10.1109/ JSSC.2003.821784

[13] E. Takeda, C. Y. Yang and A. Miura-Hamada, “Hot- Carrier Effects in MOS Devices,” Academic Press, San Diego, 1995.

[14] C. Hu and S. Tam, et al., “Hot-Electron Induced MOSFET Degrada-tion-Model, Monitor, Improvement,” IEEE Transactions on Electron Devices, Vol. ED-32, 1985, pp. 375-385.

[15] A. Hajimiri, S. Limotyrakis and T. H. Lee, “Jitter and Phase Noise in Ring Oscillators,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 6, 1999, pp. 790-804. doi:10.1109/4.766813

[16] A. Hajimiri and T. H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,” IEEE Journal of Solid- State Circuits, Vol. 33, No. 2, 1998, pp. 179-194. doi:10.11 09/4.658619

[1] G. C. Hsieh and J. C. Hung, “Phase-Locked Loop Tech- niques-A Survey,” IEEE Transactions Industrial Elec- tronics, Vol. 42, No. 6, 1996, pp. 609-615. doi:10.11 09/41.544547

[2] F. M. Gardner, “Phaselock Tech-niques,” Wiley Inter- science, Hoboken, 2005.

[3] S. L. J. Gierkink, D. Li and R. C. Frye, “A 3.5-GHz PLL for Fast Low-IF/Zero-IF LO Switching in an 802.11 Tran-sceiver,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 9, 2005, pp. 1909-1921. doi:10.1109/JSSC.200 5.848175

[4] R. E. Best, “Phase-Locked Loops-Design, Simulation, and Applications,” 6th Edition, McGraw-Hill, New York, 2007.

[5] W. Rhee, K. A. Jenkins, J. Liobe and H. Ainspan, “Experimental Analysis of Substrate Noise Effect on PLL Performance,” IEEE Transactions on Circuits and Sys- tems-II, Vol. 55, No. 7, 2008, pp. 638-642. doi:10.1109/T CSII.2008.921582

[6] C. Jeong, D. Choi and C. Yoo, “A Fast Automatic Frequency Cali-bration (AFC) Scheme for Phase-Locked Loop (PLL) Frequency Synthesizer,” Proceedings of Radio Frequency Integrated Circuits Symposium, San- Diego, 7-9 January 2009, pp. 583-586. doi:10.1109/R FIC.2009.5135609

[7] C. Hsu and Y. Lai, “Low-Cost CP-PLL DFT Structure Implementation for Digital Testing Application,” IEEE Transactions on Instrumentation and Measurement, Vol. 58, No. 6, 2009, pp. 1897-1906. doi:10.1109/TIM.200 8.2005852

[8] Y. Guo and Z. Xie, “Design of PLL Frequency Synthesizer in Frequency Hopping Communication Sy- stem,” Proceeding of In-ternational Conference on Com- munications and Mobile Computing, Shenzhen, 12-14 April 2010, pp. 138-141.

[9] E. Xiao and J. S. Yuan, “Hot Carrier and Soft Breakdown Effects on VCO Performance,” IEEE Transactions on Microwave Theory and Techniques, Vol. 50, No. 11, 2002, pp. 2453-2458. doi:10.1109/TMTT.2002.804632

[10] C. Zhang and A. Srivastava, “Hot Carrier Effects on Jitter and Phase Noise in CMOS Voltage-Controlled Oscilla- tors,” Proceedings of SPIE-Noise in Devices and Circuits III, Austin, 23-26 May 2005, pp. 52-62.

[11] C. Zhang and A. Srivastava, “Hot Carrier Effects on Jitter Performance in CMOS Voltage Controlled Oscillators,” Fluctuation and Noise Letters, Vol. 6, No. 3, 2006, pp. 329-334. doi:10.1142/S0219477506003446

[12] S. Pellerano, S. Laventin, C. Samori and A, Lacaita, “A 13.5-mW 5-GHz Frequency Synthesizer with Dynamic- logic Frequency Divider,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 2, 2004, pp. 378-383. doi:10.1109/ JSSC.2003.821784

[13] E. Takeda, C. Y. Yang and A. Miura-Hamada, “Hot- Carrier Effects in MOS Devices,” Academic Press, San Diego, 1995.

[14] C. Hu and S. Tam, et al., “Hot-Electron Induced MOSFET Degrada-tion-Model, Monitor, Improvement,” IEEE Transactions on Electron Devices, Vol. ED-32, 1985, pp. 375-385.

[15] A. Hajimiri, S. Limotyrakis and T. H. Lee, “Jitter and Phase Noise in Ring Oscillators,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 6, 1999, pp. 790-804. doi:10.1109/4.766813

[16] A. Hajimiri and T. H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,” IEEE Journal of Solid- State Circuits, Vol. 33, No. 2, 1998, pp. 179-194. doi:10.11 09/4.658619