Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study

Affiliation(s)

Faculty of Engineering, Cairo University, Cairo, Egypt.

Electronics Engineering Department, American University in Cairo, Cairo, Egypt.

Radiation Engineering Department, NCRRT, Cairo, Egypt.

College of Computing and Information Technology, AASTMT, Cairo, Egypt.

Faculty of Engineering, Cairo University, Cairo, Egypt.

Electronics Engineering Department, American University in Cairo, Cairo, Egypt.

Radiation Engineering Department, NCRRT, Cairo, Egypt.

College of Computing and Information Technology, AASTMT, Cairo, Egypt.

ABSTRACT

This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set; this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.

Cite this paper

M. Fouad, H. Amer, A. Madian and M. Abdelhalim, "Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study,"*Circuits and Systems*, Vol. 4 No. 4, 2013, pp. 364-368. doi: 10.4236/cs.2013.44049.

M. Fouad, H. Amer, A. Madian and M. Abdelhalim, "Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study,"

References

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[5] A. H. Madian, H. H. Amer and A. O. Eldesouky, “Catas trophic Short and Open Fault Detection in MOS Current Mode Circuits: A Case Study,” Proceedings of the 12th Biennial Baltic Electronics Conference BEC, Tallinn, 2010, pp. 145-148. doi:10.1109/BEC.2010.5631512

[6] M. M. Fouad, A. H. Madian, H. H. Amer and M. B. Ab delHalim, “Low Cost Test for Catastrophic Faults in CMOS Operational Transconductor,” Proceedings of the International Conference on Microelectronics ICM, Hammamet, 19-22 December 2011, pp. 1-5. doi:10.1109/ICM.2011.6177397

[7] N. Nagi and J. A. Abraham, “Hierarchical Fault Modeling for Linear Analog Circuits,” Analog Integrated Circuits and Signal Processing, Vol. 10, No. 1-2, 1996, pp. 89-99. doi:10.1007/BF00713981

[8] T. Olbrich, J. Perez, I. A. Grout, A. M. D. Richardson and C. Ferrer, “Defect-Oriented vs Schematic-Level Based Fault Simulation for Mixed-Signal ICs,” Proceedings of the IEEE International Test Conference, Washington DC, 20-25 October 1996, pp. 511-520.

[9] W. Al-Asssadi and P. Chandrasekhar, “Issues in Testing Analog Devices,” Proceedings of the 12th NASA Symposium on VLSI, Coeur d’Alene, 2005.

[10] V. Srinivasan, D. Sam Ha and J. B. Sulistyo, “Gigahertz range MCML Multiplier Architecture,” Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. 2, Vancouver, 2004, pp. 785-788.

[11] “Mentor Graphics Website,” 2013. http://www.mentor.com/products/ic_nanometer_design/analog-mixed-signal-verification/eldo/

[12] S. Goel, M. Elgamel, M. Bayoumi and Y. Hanafy, “Design Methodologies for High-Performance Noise-Tolerant XOR-XNOR Circuits,” IEEE Transactions on Circuits and Systems I, Vol. 53, No. 4, 2006, pp. 867-878. doi:10.1109/TCSI.2005.860119

[1] J. Rabaey, “Digital Integrated Circuits: A Design Perspective,” Prentice-Hall, Upper Saddle River, 1996.

[2] P. Gray, P. Hurst, S. Lewis and R. Meyer, “Analysis and Design of Analog Integrated Circuits,” 4th Edition, John Wiley & Sons, New York, 2000.

[3] B. Razavi, “Prospects of CMOS Technology for High Speed Optical Communication Circuits,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 9, 2002, pp. 1135-1145. doi:10.1109/JSSC.2002.801195

[4] M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono and H. Yamada, “A GHz MOS Adaptive Pipeline Technique Using MOS Current-Mode Logic,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 6, 1996, pp. 784-791. doi:10.1109/4.509864

[5] A. H. Madian, H. H. Amer and A. O. Eldesouky, “Catas trophic Short and Open Fault Detection in MOS Current Mode Circuits: A Case Study,” Proceedings of the 12th Biennial Baltic Electronics Conference BEC, Tallinn, 2010, pp. 145-148. doi:10.1109/BEC.2010.5631512

[6] M. M. Fouad, A. H. Madian, H. H. Amer and M. B. Ab delHalim, “Low Cost Test for Catastrophic Faults in CMOS Operational Transconductor,” Proceedings of the International Conference on Microelectronics ICM, Hammamet, 19-22 December 2011, pp. 1-5. doi:10.1109/ICM.2011.6177397

[7] N. Nagi and J. A. Abraham, “Hierarchical Fault Modeling for Linear Analog Circuits,” Analog Integrated Circuits and Signal Processing, Vol. 10, No. 1-2, 1996, pp. 89-99. doi:10.1007/BF00713981

[8] T. Olbrich, J. Perez, I. A. Grout, A. M. D. Richardson and C. Ferrer, “Defect-Oriented vs Schematic-Level Based Fault Simulation for Mixed-Signal ICs,” Proceedings of the IEEE International Test Conference, Washington DC, 20-25 October 1996, pp. 511-520.

[9] W. Al-Asssadi and P. Chandrasekhar, “Issues in Testing Analog Devices,” Proceedings of the 12th NASA Symposium on VLSI, Coeur d’Alene, 2005.

[10] V. Srinivasan, D. Sam Ha and J. B. Sulistyo, “Gigahertz range MCML Multiplier Architecture,” Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. 2, Vancouver, 2004, pp. 785-788.

[11] “Mentor Graphics Website,” 2013. http://www.mentor.com/products/ic_nanometer_design/analog-mixed-signal-verification/eldo/

[12] S. Goel, M. Elgamel, M. Bayoumi and Y. Hanafy, “Design Methodologies for High-Performance Noise-Tolerant XOR-XNOR Circuits,” IEEE Transactions on Circuits and Systems I, Vol. 53, No. 4, 2006, pp. 867-878. doi:10.1109/TCSI.2005.860119