This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set; this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.
Cite this paper
M. Fouad, H. Amer, A. Madian and M. Abdelhalim, "Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study," Circuits and Systems
, Vol. 4 No. 4, 2013, pp. 364-368. doi: 10.4236/cs.2013.44049
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