Since in designing the full adder circuits, full adders
have been generally taken into account, so as in this paper it has been
attempted to represent a full adder cell with a significant efficiency of
power, speed and leakage current levels. For this objective, a comparison
between five full adder circuits has been provided. Applying floating gate
technology and refresh circuits in the full adder cell lead to the reduction of
leakage current on the gate node. The simulations were accomplished in this
paper, through HSPICE software and 65 nm CMOS technology. The simulation
results indicate the considerable efficiency of power consumption, speed and
leakage current in the full adder cell rather than other cells.
Cite this paper
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