Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

Author(s)
Omnia S. Ahmed,
Mohamed F. Abu-Elyazeed,
Mohamed B. Abdelhalim,
Hassanein H. Amer,
Ahmed H. Madian

Affiliation(s)

Faculty of Engineering, Cairo University, Giza, Egypt.

College of Computing and Information Technology, Arab Academy for Science, Technology & Maritime Transport, Cairo, Egypt.

Electronics Engineering Department, American University in Cairo, Cairo, Egypt.

Radiation Engineering Department, Egyptian Atomic Energy Authority, Cairo, Egypt.

Faculty of Engineering, Cairo University, Giza, Egypt.

College of Computing and Information Technology, Arab Academy for Science, Technology & Maritime Transport, Cairo, Egypt.

Electronics Engineering Department, American University in Cairo, Cairo, Egypt.

Radiation Engineering Department, Egyptian Atomic Energy Authority, Cairo, Egypt.

ABSTRACT

In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.

In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.

KEYWORDS

Dynamic Power Estimation; Logic Pictures; CMOS Digital Logic Circuits; Toggle Rate; Unit-Delay Model

Dynamic Power Estimation; Logic Pictures; CMOS Digital Logic Circuits; Toggle Rate; Unit-Delay Model

Cite this paper

Ahmed, O. , Abu-Elyazeed, M. , Abdelhalim, M. , Amer, H. and Madian, A. (2013) Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits.*Circuits and Systems*, **4**, 276-279. doi: 10.4236/cs.2013.43037.

Ahmed, O. , Abu-Elyazeed, M. , Abdelhalim, M. , Amer, H. and Madian, A. (2013) Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits.

References

[1] G. Theodoridis, S. Theoharis, D. Soudris and C. Goutis, “An Efficient Probabilistic Method for Logic Circuits using Real Gate Delay Model,” Proceedings of the International Symposium on Circuits and Systems ISCAS, Orlando, 30 May-2 June 1999, pp. 286-289.

[2] S. Bhanja and N. Ranganathan, “Switching Activity Estimation of VLSI Circuits Using Bayesian Networks” IEEE Transactions on VLSI Systems, Vol. 11, No. 4, 2003, pp. 558-567. doi:10.1109/TVLSI.2003.816144

[3] M. Xakellis and F. Najm, “Statistical Estimation of the Switching Activity in Digital Circuits,” Proceedings of the Conference on Design Automation DAC, San Diego, 6-10 June 1994, pp. 728-733.

[4] M. Nemani and F. Najm, “Towards a High-Level Power Estimation Capability,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, Vol. 15, No. 6, 1996, pp. 588-598. doi:10.1109/43.503929

[5] A. Ghosh, S. Devadas, K. Keutzer and J. White, “Estimation of Average Switching Activity in Combinational and Sequential Circuits,” Proceedings of the Conference on Design Automation DAC, Anaheim, 8-12 June 1992, pp. 253-259.

[6] C. S. Ding, C. Y. Tsui and M. Pedram, “Gate-Level Power Estimation Using Tagged Probabilistic Simulation,” IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, Vol. 17, No. 11, 1998, pp. 1099-1107. doi:10.1109/43.736184

[7] S. M. Kang, “Accurate Simulation of Power Dissipation in VLSI Circuits,” IEEE Transactions on Solid-State Circuits, Vol. 21, No. 5, 1986, pp. 889-891. doi:10.1109/JSSC.1986.1052622

[8] R. Burch, F. N. Najm, P. Yang and T. N. Trich, “A Monte Carlo Approach for Power Estimation,” IEEE Transactions on VLSI Systems, Vol. 1, No. 1, 1993, pp. 63-71. doi:10.1109/92.219908

[9] J. Monteiro, S. Daved, A. Chos, K. Keutzer and J. White, “Estimation of Average Switching Activity in Combinational Logic Circuits Using Symbolic Simulation,” IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, Vol. 16, No. 1, 1997, pp. 121-127. doi:10.1109/43.559336

[10] M. F. Fouda, M. B. Abdelahlim and H. H. Amer, “Average and Maximum Power Consumption of Digital CMOS Circuits Using Logic Pictures,” Proceedings of the International Conference on Computer Engineering and Systems ICCES, Cairo, 14-16 December 2009, pp. 14-16.

[11] M. F. Fouda, M. B. Abdelahlim and H. H. Amer, “Power Consumption of Sequential CMOS Circuits Using Logic Pictures,” Proceedings of the Biennial Baltic Electronics Conference BEC, Tallinn, 4-6 October 2010, pp. 133-136.

[12] M. H. Amin, M. F. Fouda, A. M. Eltantawy, M. B. Abdelahlim and H. H. Amer, “Generalization of Logic Picture-Based Power Estimation Tool,” Proceedings of the First Annual International Conference on Energy Aware Computing ICEAC, Cairo, 16-18 December 2010, pp. 133-136.

[13] F. Najm, “A Survey of Power Estimation Techniques in VLSI Circuits,” IEEE Transactions on VLSI Systems, Vol. 2, No. 4, 1994, pp. 446-455. doi:10.1109/92.335013

[14] F. Najm, “Transition Density: A New Measure of Activity in Digital Circuits,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, Vol. 12, No. 2, 1993, pp. 310-323. doi:10.1109/43.205010

[1] G. Theodoridis, S. Theoharis, D. Soudris and C. Goutis, “An Efficient Probabilistic Method for Logic Circuits using Real Gate Delay Model,” Proceedings of the International Symposium on Circuits and Systems ISCAS, Orlando, 30 May-2 June 1999, pp. 286-289.

[2] S. Bhanja and N. Ranganathan, “Switching Activity Estimation of VLSI Circuits Using Bayesian Networks” IEEE Transactions on VLSI Systems, Vol. 11, No. 4, 2003, pp. 558-567. doi:10.1109/TVLSI.2003.816144

[3] M. Xakellis and F. Najm, “Statistical Estimation of the Switching Activity in Digital Circuits,” Proceedings of the Conference on Design Automation DAC, San Diego, 6-10 June 1994, pp. 728-733.

[4] M. Nemani and F. Najm, “Towards a High-Level Power Estimation Capability,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, Vol. 15, No. 6, 1996, pp. 588-598. doi:10.1109/43.503929

[5] A. Ghosh, S. Devadas, K. Keutzer and J. White, “Estimation of Average Switching Activity in Combinational and Sequential Circuits,” Proceedings of the Conference on Design Automation DAC, Anaheim, 8-12 June 1992, pp. 253-259.

[6] C. S. Ding, C. Y. Tsui and M. Pedram, “Gate-Level Power Estimation Using Tagged Probabilistic Simulation,” IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, Vol. 17, No. 11, 1998, pp. 1099-1107. doi:10.1109/43.736184

[7] S. M. Kang, “Accurate Simulation of Power Dissipation in VLSI Circuits,” IEEE Transactions on Solid-State Circuits, Vol. 21, No. 5, 1986, pp. 889-891. doi:10.1109/JSSC.1986.1052622

[8] R. Burch, F. N. Najm, P. Yang and T. N. Trich, “A Monte Carlo Approach for Power Estimation,” IEEE Transactions on VLSI Systems, Vol. 1, No. 1, 1993, pp. 63-71. doi:10.1109/92.219908

[9] J. Monteiro, S. Daved, A. Chos, K. Keutzer and J. White, “Estimation of Average Switching Activity in Combinational Logic Circuits Using Symbolic Simulation,” IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, Vol. 16, No. 1, 1997, pp. 121-127. doi:10.1109/43.559336

[10] M. F. Fouda, M. B. Abdelahlim and H. H. Amer, “Average and Maximum Power Consumption of Digital CMOS Circuits Using Logic Pictures,” Proceedings of the International Conference on Computer Engineering and Systems ICCES, Cairo, 14-16 December 2009, pp. 14-16.

[11] M. F. Fouda, M. B. Abdelahlim and H. H. Amer, “Power Consumption of Sequential CMOS Circuits Using Logic Pictures,” Proceedings of the Biennial Baltic Electronics Conference BEC, Tallinn, 4-6 October 2010, pp. 133-136.

[12] M. H. Amin, M. F. Fouda, A. M. Eltantawy, M. B. Abdelahlim and H. H. Amer, “Generalization of Logic Picture-Based Power Estimation Tool,” Proceedings of the First Annual International Conference on Energy Aware Computing ICEAC, Cairo, 16-18 December 2010, pp. 133-136.

[13] F. Najm, “A Survey of Power Estimation Techniques in VLSI Circuits,” IEEE Transactions on VLSI Systems, Vol. 2, No. 4, 1994, pp. 446-455. doi:10.1109/92.335013

[14] F. Najm, “Transition Density: A New Measure of Activity in Digital Circuits,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, Vol. 12, No. 2, 1993, pp. 310-323. doi:10.1109/43.205010