A New Technique for Leakage Reduction in 65 nm Footerless Domino Circuits

Affiliation(s)

Department of Electronics & Communication, Maulana Azad National Institute of Technology, Bhopal, India.

Department of Electronics & Communication, Maulana Azad National Institute of Technology, Bhopal, India.

ABSTRACT

A new circuit technique for 65 nm technology is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this technique a *p*-type and an *n*-type leakage controlled transistors (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. For any combination of input, one of the LCT will operate near its cut off region and will increase the resistance between supply voltage and ground resulting in reduced leakage current. Furthermore, the leakage current is suppressed at the output inverter circuit by inserting a transistor below the *n*-type transistor of the inverter offering more resistive path between supply voltage and ground. The proposed technique is applied on benchmark circuits reduction of active power consumption is observed from 10.9% to 44.76% at different temperature variations. For same benchmark circuits, operating at two clock modes and giving low and high inputs at 25℃ and 110℃ temperatures the maximum leakage power saving of 98.9% is achieved when compared to standard footerless domino logic circuits.

Cite this paper

T. Gupta and K. Khare, "A New Technique for Leakage Reduction in 65 nm Footerless Domino Circuits,"*Circuits and Systems*, Vol. 4 No. 2, 2013, pp. 209-216. doi: 10.4236/cs.2013.42028.

T. Gupta and K. Khare, "A New Technique for Leakage Reduction in 65 nm Footerless Domino Circuits,"

References

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[12] F. Moradi and A. Peiravi, “An Improved Noise—Tolerant Domino Logic Circuit for High Fan-In Gates,” IEEE Pro ceedings, 2005, pp. 116-121.

[13] M. C. Johnson, D. Somasekhar, L. Y. Chiou and K. Roy, “Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 10, No. 1, 2002, pp. 1-5. doi:10.1109/92.988724

[14] S. Narendra, S. Borkar, V. De, D. Antoniadis and A. P. Chandrakasan, “Scaling of Stack Effect and Its Application for Leakage Reduction,” IEEE International Symposium on Low Power Electronics and Design, August 2001, pp. 195-200.

[15] S. Sirichotiyakul, T. Edwards, C. Oh, R. Panda and D. Blaauw, “Duet: An Accurate Leakage Estimation and Op timization Tool for Dual-Vt Circuits,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 10, No. 2, 2002, pp. 79-90. doi:10.1109/92.994980

[1] H. Mahmoodi-Meimand and K. Roy, “A Leakage-Toler ant High Fan-in Dynamic Circuit Style,” IEEE Interna tional Systems-on-Chip Conference, 17-20 September 2003, pp. 117-120. doi:10.1109/SOC.2003.1241475

[2] J.-S. Wang, S.-J. Shieh, C. Yeh and Y.-H. Yeh, “Pseudo Footless CMOS Domino Logic Circuits for High-Per formance VLSI Designs,” IEEE International Symposium on Circuits and Systems, Hiroshima, 25-28 July 2004, pp. 401-404.

[3] V. Kursun and E. G. Friedman, “Domino Logic with Va riable Threshold Voltage Keeper,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 6, 2003, pp. 1080-1093.

[4] Y. Taur and T. H. Hing, “Fundamentals of Modern VLSI Devices,” Cambridge University Press, New York, 1998, pp. 120-128.

[5] K. Roy, et al., “Leakage Current Mechanisms and Leak age Reduction Techniques in Deep-Submicrometer CMOS Circuits,” IEEE Proceedings, Vol. 91, No. 2, 2003, pp. 306-327. doi:10.1109/JPROC.2002.808156

[6] Y. Taur and T. H. Hing, “Fundamentals of Modern VLSI Devices,” Cambridge University Press, New York, 1998, pp. 94-95.

[7] Y. Taur and T. H. Hing, “Fundamentals of Modern VLSI Devices,” Cambridge University Press, New York, 1998, pp. 97-99.

[8] K. Roy and S. C. Prasad, “Low-Power CMOS VLSI Circuit Design,” Wiley Interscience Publications, New York, 2000, pp. 28-29.

[9] K. Roy and S. C. Prasad, “Low-Power CMOS VLSI Circuit Design,” Wiley Interscience Publications, New York, 2000, pp. 27-28.

[10] Z. Liu and V. Kursun, “Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies,” Transactions on Circuits and Systems Part II—Express Briefs, Vol. 53, No. 8, 2006, pp. 692-696.

[11] H. Sasaki, M. Ono, T. Ohguro, S. Nakamura, M. Satio and Iwai, “1.5 nm Direct-Tuneling Gate Oxide Si MOS FETs,” IEEE Transactions on Electron Devices, Vol. 43, No. 8, 1996, pp. 1233-1242.

[12] F. Moradi and A. Peiravi, “An Improved Noise—Tolerant Domino Logic Circuit for High Fan-In Gates,” IEEE Pro ceedings, 2005, pp. 116-121.

[13] M. C. Johnson, D. Somasekhar, L. Y. Chiou and K. Roy, “Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 10, No. 1, 2002, pp. 1-5. doi:10.1109/92.988724

[14] S. Narendra, S. Borkar, V. De, D. Antoniadis and A. P. Chandrakasan, “Scaling of Stack Effect and Its Application for Leakage Reduction,” IEEE International Symposium on Low Power Electronics and Design, August 2001, pp. 195-200.

[15] S. Sirichotiyakul, T. Edwards, C. Oh, R. Panda and D. Blaauw, “Duet: An Accurate Leakage Estimation and Op timization Tool for Dual-Vt Circuits,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 10, No. 2, 2002, pp. 79-90. doi:10.1109/92.994980