K. Bard, B. Dewey, M.-T. Hsu, T. Mitchell, K. Moody, V. Rao, R. Rose, J. Soreff and S. Washburn, “Transistor Level Tools for High-End Processor Custom Circuit De sign at IBM,” IEEE Proceedings of the Journal, Vol. 95, No. 3, 2007, pp. 530-554. doi:10.1109/JPROC.2006.889385
 Z. T. Li and S. M. Chen, “Transistor Level Timing Analysis Considering Multiple Inputs Simultaneous Swi tching,” IEEE Proceedings of 10th Computer-Aided De sign and Computer Graphics, Beijing, October 2007, pp. 315-320.
 C. H. Chen, X. J. Yang and M. Sarrafzadeh, “Potential Slack: An Effective Metric of Combinational Circuit Per formance,” IEEE International Conference on Computer Aided Design, San Jose, 5-9 November 2000, pp. 198-201.
 F. Sill and F. G. D. Timmermann, “Total Leakage Power Optimization with Improved Mixed Gates,” Proceedings of the 18th Symposium on Integrated Circuits and System Design, Florianolpolis, 4-7 September 2005, pp. 154-159.
 R. Nair, C. L. Berman, P. S. Hauge and E. J. Yoffa, “Ge neration of Performance Constraints for Layout,” IEEE Transactions on Computer-Aided Design, Vol. 8, No. 8, 1989, pp. 860-874. doi:10.1109/43.31546
 T. Gao, P. M. Vaidya and C. L. Liu, “A New Perfor mance Driven Placement Algorithm,” Proceedings of IEEE International Conference on Computer Aided Design, Santa Clara, 11-14 November 1991, pp. 44-47.
 S. Dutta, S. Nag and K. Roy, “ASAP: A Transistor Sizing Tool for Speed, Area, and Power Optimization of Static CMOS Circuits,” International Symposium of Circuits and Systems, London, 30 May-2 June 1994, pp. 61-64.
 H.-Y. Song, K. Nepal, R. I. Bahar and J. Grodstein “Timing Analysis for Full-Custom Circuits Using Sym bolic DC Formulations,” IEEE Transactions on Com puter-Aided Design Integral Circuits Systems, Vol. 25, No. 9, 2006, pp. 1815-1830.
 B. Rich.man, J. Hansen and K. Cameron, “A Determinis tic Algorithm for Automatic CMOS Transistor Sizing,” IEEE Proceedings of Conference on Custom Integmted Circuits Conference, Portland, 4-7 May 1987, pp. 421-424.
 S. Raja, F. Varadi, M. Becer and J. Geada, “Transistor Level Gate Modeling for Accurate and Fast Timing, Noise, and Power Analysis,” Proceedings of Design Automation Conference, Anaheim, 8-13 June 2008.
 R. Rogenmoser and Kaeslin, “The Impact of Transistor Sizing on Power Efficiency in Submicron CMOS Cir cuits,” IEEE Journal of Solid-State Circuits and systems, Vol. 32, No. 7, 1997, pp. 1142-1145.
 D. Blaauw, K. Chopra, A. Srivastava and L. Scheffer, “Statistical Timing Analysis: From Basic Principles to State of the Art,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 4, 2008, pp. 589-607. doi:10.1109/TCAD.2007.907047
 A. Dendouga, N. Bouguechal, S. Barra and O. Manck, “Timing Characterization and Layout of a Low Power Differential C2MOS Flip-Flop in 0.35 μm Technology,” 2nd International Conference on Electrical Engineering Design and Technologies, Hammamet, 8-10 November 2008, pp. 1-4.
 P. Y. Calland, A. Mignotte, O. Peyran, Y. Robert and F. Vivien, “Retiming DAG’s (Direct Acyclic Graph),” IEEE Transaction on Computer-Aided Design Integrated Cir cuits and Systems, Vol. 17, No. 12, 1998, pp. 1319-1325. doi:10.1109/43.736571
 K. Choi and A. Chatterjee, “PA-ZSA (Power Aware Zero Slack Algorithm): A Graph Based Timing Analysis for Ultra Low-Power CMOS VLSI,” Proceedings of the Power and Timing Modeling, Optimization and Simula tion, Seville, 11-13 September 2002, pp. 178-187.
 A. Rjoub and A. B. Alajlouni, “Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits,” IEEE Proceedings of the 16th Mediterranean Electrotechnical, Yasmine Hammamet, 25-28 March 2012, pp. 80-83.