This paper investigates the threshold voltage sensitivity to metal gate work-function for n-channel double gate fin field-effect transistor (FinFET) structures and evaluates the short channel performance of the device using threshold voltage dependence on metal gate work-function analysis. We carried out the study for a double gate n-channel fin field-effect transistor (n-FinFET) with parameters as per the projection report of International Technology Roadmap for Semiconductors, ITRS-2011 for low standby power (LSTP) 20 nm gate length technology node. In the present study device simulation have been carried out using PADRE simulator from MuGFET, which is based on the drift-diffusion theory. Our results show the accuracy and validity of classical drift-diffusion simulation results for transistor structures with lateral dimensions 10nm and above. The subthreshold behavior of device improves with increased metal gate work-function. The results also show that a higher gate work-function (≥5 eV) can fulfill the tolerable off-current as projected in ITRS 2011 report. The SCE in FinFET can reasonably be controlled and improved by proper adjustment of the metal gate work-function. DIBL is reduced with the increase in gate work function.
Cite this paper
M. Mustafa, T. Bhat and M. Beigh, "Threshold Voltage Sensitivity to Metal Gate Work-Function Based Performance Evaluation of Double-Gate n-FinFET Structures for LSTP Technology," World Journal of Nano Science and Engineering
, Vol. 3 No. 1, 2013, pp. 17-22. doi: 10.4236/wjnse.2013.31003
 “International Technology Roadmap for Semiconductors,” 2011. http://www.itrs.net
 D. Hisamoto, T. Kaga, Y. Kawamo and E. Takeda, “A Fully Depleted Lean-Channel Transistor (DELTA)—A Novel Vertical Ultra Thin SOI MOSFET,” Technical Digest of IEDM, Washington, DC, 3-6 December 1989, pp. 833-836
 D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor and C. M. Hu, “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, Vol. 47, No. 12, 2000, pp. 2320-2325.
 M.-H. Chiang, C.-N. Lin and G.-S. Lin, “Threshold Voltage Sensitivity to Doping Density in Extremely Scaled MOSFETs,” Semiconductor Science and Technology, Vol. 21, No. 2, 2006, pp. 190-193.
 S. Xiong and J. Bokor, “Sensitivity of Double-Gate and FinFET Devices to Process Variations,” IEEE Transactions on electron Devices, Vol. 50, No. 11, 2003, pp. 2255-2260. doi:10.1109/TED.2003.818594
 K.-R. Han, B.-K. Choi, H.-I. Kwoni and J.-H. Lee, “Design of Bulk Fin-Type Field-Effect Transistor Considering Gate Work-Function,” Japanese Journal of Applied Physics, Vol. 47, No. 6, 2008, pp. 4385-4391.
 I. De, D. Johri, A. Srivastava and C. M. Osburn, “Impact of Gate Workfunction on Device Perfor??mance at the 50 nm Technology Node,” Solid-State Electronics, Vol. 44, No. 6, 2000, pp. 1077-1080.
 C. J. Choi, M. Y. Jang, Y. Y. Kim, M. S. Jun, T. Y. Kim, B. C. Park, S. J. Lee, H. D. Yang, R. J. Jung, M. Chang, and H. S. Hwang, “Effective Metal Work Function of High-Pressure Hydrogen Postannealed Pt-Er Alloy Metal Gate on HfO2 Film,” Japanese Journal of Applied Physics, Vol. 46, No. 1, 2007, pp. 125-127.
 R. J. P. Lander, J. C. Hooker, J. P. van Zijl, F. Roozeboom, M. P. M. Maas, Y. Tamminga and R. A. M. Wolters, “A Tuneable Metal Gate Work Function Using Solid State Diffusion of Nitrogen,” ESSDERC, Florence, 24-26 September 2002, pp. 103-106.
 M. C. Lemme, J. K. Efavi, H. D. B. Gottlob, T. Mollenhauer, T. Wahlbrink and H. Kurz, “Comparison of Metal Gate Electrodes on MOCVD HfO2,” Microelectronics Reliability, Vol. 45, No. 5-6, 2005, pp. 953-956.
 R. Lin, Q. Lu, P. Ranade, T.-J. King and C. M. Hu, “An Adjustable Work Function Technology Using Mo Gate for CMOS Devices,” IEEE Electron Device Letters, Vol. 23, No. 1, 2002, pp. 49-51.
 G. Sjoblom, “Metal Gate Technology for Advanced CMOS Devices,” Ph.D. Dissertation, Uppsala University, Uppsala, 2006.
 J.-P. Collinge, “FinFET and Other Multi-Gate Transistors,” Springer, Berlin, 2008.
 “MuGFET v 1.1, Simulation tool for Nanoscale Multigate-FET Structures (FinFET and Nanowire).”
 “First Time User Guide (FTUG) to MuGFET v 1.1.”
 T.-S. Park, E. J. Yoon and J.-H. Lee, “A 40 nm BodyTied FinFET (OMEGA MOSFET) Using Bulk Si Wafer,” Physica E: Low-Dimensional Systems and Nanostructures, Vol. 19, No. 1-2, 2003, pp. 6-12.
 Y.-K. Choi, T.-J. King and C. M. Hu, “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, Vol. 23, No. 1, 2002. pp. 25-27.