This paper presents the design of an ultra low-voltage (ULV) pseudo operational transconductance amplifier (P-OTA) that is able to operate with a single supply voltage as low as 0.4 V. The proposed circuit is based on the bulk-driven technique and use of cross-coupled self-cascode pairs that boosts the differential DC gain. The stability condition of this structure for the DC gain is considered by definition of two coefficients to cancel out a controllable percentage of the denominator. This expression for stability condition yield optimized value for the DC gain. Also, as the principle of operation of the proposed technique relies on matching conditions, Monte Carlo analyzes are considered to study of the behavior of the proposed circuit against mismatches. The designed P-OTA have a DC gain of 64 dB, 212 KHz unity gain bandwidth, 57phase margin that is loaded by 10 pF differential capacitive loads, while consume only 16 μW. Eventually, from the proposed P-OTA, a low-power Sample and Hold (S/H) circuit with sampling frequency of 10 KS/s has been designed and simulated. The correct functionality for this configuration is verified from –30℃ to 70℃. The simulated data presented is obtained using the HSPICE Environment and is valid for the 90 nm triple-well CMOS process.
 S. Yan and E. Sanchez-Sinencio, “Low-Voltage Analog Circuit Design Techniques: A Tutorial,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer, Vol. 83, No. 2, 2000, pp. 179-196.
 J. Ramirez-Angulo, R. G. Carvajal and A. Torralba, “Low Supply Voltage High Performance CMOS Current Mirror with Low Input and Output Voltage Requirements,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 51, No. 3, 2004, pp. 124-129. doi:10.1109/TCSII.2003.822429
 ITRS, “The International Technology Roadmap for Semiconductors,” 2008. http://public.itrs.net
 A. Baschirotto, V. Chironi, G. Cocciolo, S. D’Amico, M. De Matteis and P. Delizia, “Low Power Analog Design in Scaled Technologies,” Topical Workshop on Electronics for Particle Physics, Pairs, 21-25 September 2009, pp. 103-110.
 J. Pekarik, D. Greenberg, B. Jagannathan, R. Groves, J. R. Jones, R. Singh, A. Chinthakindi, X. Wang, M. Breitwisch, D. Coolbaugh, P. Cottrell, J. Florkey, G. Freeman and R. Krishnasamy, “RFCMOS Technology from 0.25 nm to 65 nm: The State of the Art,” Proceedings of the IEEE Custom Integrated Circuits Conference, 3-6 October 2004, pp. 217-224.
 M. Trakimas and S. Sonkusale, “A 0.5 V Bulk-Input OTA with Improved Common-Mode Feedback for Low-Frequency Filtering Applications,” Analog Integrated Circuits and Signal Processing, Vol. 59, No. 1, 2009, pp. 83-89. doi:10.1007/s10470-008-9236-z
 A. Guzinski, M. Bialko and J. C. Matheau, “Body-Driven Differential Amplifier for Application in Continous-Time Active-C Filter,” Proceedings of the European Conference on Circuit Theory and Design, June 1987, pp. 315-319.
 J. M. Carrillo, G. Torelli and J. F. Duque-Carrillo, “Transconductance Enhancement in Bulk-Driven Input Stages and Its Applications,” Analog Integrated Circuits and Signal Processing, Vol. 68, No. 2, 2011, pp. 207-217. doi:10.1007/s10470-011-9603-z
 L. H. C. Ferreira, T. C. Pimenta and R. L. Moreno, “An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA with Rail-to-Rail Input/Output Swing,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 54, No. 10, 2007, pp. 843-847. doi:10.1109/TCSII.2007.902216
 J. M. Carrillo, G. Torelli, R. Pérez-Aloe and J. F. Duque-Carrillo, “1-V Rail-to-Rail CMOS Opamp with Improved Bulk-Driven Input Stage,” IEEE Journal of Solid-State Circuits, Vol. 42, No. 3, 2007, pp. 508-517.
 H. Khameh and H. Shamsi, “A Sub-1 V High-Gain Two-Stage OTA Using Bulk-Driven and Positive Feedback Techniques,” 5th European Conference on Circuits and Systems for Communications, Serbia, November 2010.
 S. Chatterjee, Y. Tsvidis and P. Kinget, “0.5 V Analog Circuit Techniques and Their Application to OTA and Filter Design,” IEEE Journal of Solid State Circuits, Vol. 40, No. 12 , 2005, pp. 2373-2387. doi:10.1109/JSSC.2005.856280
 A. N. Mohieldin, “High Performance Continuous-Time Filters for Information Transfer Systems,” Ph.D. Dissertation, Department of Electrical Engineering, Texas A&M University, College Station, 2003.
 A. Ahmadpour, “A 0.4 V Bulk-Input Pseudo Amplifier in 90 nm CMOS Technology,” Proceeding of 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, 14-16 April 2010, pp. 301-304.
 M.-J. Chen, J.-S. Ho, T.-H. Huang, C.-H. Yang, Y.-N. Jou and T. Wu, “Back-Gate Forward Bias Method for Low-Voltage CMOS Digital Circuits,” IEEE Transactions on Electron Devices, Vol. 43, No. 6, 1996, pp. 904-910. doi:10.1109/16.502122
 S. Narendra, J. Tschanz, J. Hofsheier, B. Bloechel, S. Vangal, Y. Hoskote, S. Tang, D. Somasekhar, A. Keshavarzi, V. Erraguntla, G. Dermer, N. Borkar, S. Borkar and V. De, “Ultra-Low Voltage Circuits and Processor in 180 nm to 90 nm Technologies with a Swapped-Body Biasing Technique,” IEEE International Digest of Technical Papers. Solid-State Circuits Conference, Vol. 1, 2004, pp. 156-157.
 J. W. Tschanz, J. T. Kao, S. Narendra, R. Nair, D. Antoniadis and A. P. Chandrakasan, “Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, 2002, pp. 1396-1402. doi:10.1109/JSSC.2002.803949
 V. R. Kaenel, M. D. Pardoen, E. Dijkstra and E. A. Vittoz, “Automatic Adjustment of Threshold and Supply Voltages for Minimum Power Consumption in CMOS Digital Circuits,” IEEE Symposium Digest of Technical Papers. Low Power Electronics, San Diego, 10-12 October 1994, pp. 78-79. doi:10.1109/LPE.1994.573211
 J. Crols and M. Steyaert, “Switched-Opamp: An Approach to Realize Full CMOS Switched-Capacitor Circuits at Very Low Power-Supply Voltages,” IEEE Journal of Solid-State Circuits, Vol. 29, No. 8, 1994, pp. 936-942. doi:10.1109/4.297698
 J.-T. Wu, Y.-H. Chang and K. L. Chang, “1.2 V CMOS Switched-Capacitor Circuits,” IEEE International Digest of Technical Papers. Solid-State Circuits Conference, San Francisco, 8-10 February 1996, pp. 388-389.
 T. Brooks, D. Robertson, D. Kelly, A. D. Muro and S. Harston, “A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25 MHZ Signal Bandwidth and 89 dB SNR,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 12, 1997, pp. 1896-906.doi:10.1109/4.643648
 M. Dessouky and A. Kaiser, “A 1-V 1-mW Digital-Audio Modulator with 88-dB Dynamic Range Using Local Switch Bootstrapping,” Proceedings of the IEEE Custom Integrated Circuits Conference, Orlando, 21-24 May 2000, pp. 13-16.
 U. Moon, G. Temes, E. Bidari, M. Keskin, L. Wu, J. Steensgaard and F. Maloberti, “Switched-Capacitor Circuit Techniques in Submicron Low-Voltage CMOS,” 6th International Conference on VLSI and CAD, Seoul, 26-27 October 1999, pp. 349-358.