Z. H. Gao, Y. C. Li and S. L. Yan, “A 0.4 ps-RMS-Jitter 1-3 GHz Ring Oscillator PLL Using Phase-Noise Preamplification,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 9, 2008, pp. 2079-2089. doi:10.1109/JSSC.2008.2001873
 G. Manganaro, S. UngKwak, S. H. Cho and A. Pulincherry, “A Behavioral Modelling Approach to the Design a Low Jitter Clock Source,” IEEE Transactions on Circuit and Systems II, Vol. 50, No. 11, 2003, pp. 804-814.
 L. Bizjak, N. Da Dalt, P. Thurner, R. Nonis, P. Paletri and L. Selmi, “Comprehensive Behavioral Modeling of Conventional and Dual-Tunig PLLs,” IEEE Transactions on Circuit and System I, Vol. 55,No. 6, 2008, pp. 1628-1638.
 S. Brigati, F. Francesconi, A. Malvasi, A. Pesucci and M. Polerri, “Modeling of Franctional-N Division Frequency Synthesizers with Simulink and Matlab,” The 8th IEEE International Conference on Electronics, Circuits and Systems, Vol. 2, 2001, pp. 1081-1084.
 M. H. Perrott, “Fast and Accurate Behaviotal Simulation of Fractional-N Frequency Synthesizers and Other PLL/DLL Circuits,” Proceedings of the 39th annual Design Automation Conference, New York, 10-14 June 2002, pp. 498-503.
 R. B. Staszewski, C. Fernando and P. T. Balsara, “Event-Driven Simulation and Modeling of Phase Noise of an RF Oscillator,” IEEE Transactions on Circuit and Systems I, Vol. 52, No. 4, 2005, pp. 723-733.
 D. A. Badillo and S. Kiaei, “A Low Phase Noise 2.0 V 900 MHz CMOS Voltage Controlled Ring Oscillator,” Proceedings of the 2004 International Symposium on Circuits and Systems, Vol. 4, 2004, p. 533
 K. Li, R. Wilcock and P. Wilson, “Improved 6.7 GHz CMOS VCO Delay Cell with up to Seven Octave Tuning Range,” IEEE International Symposium on Circuits and Systems, Seattle, 18-21 May 2008, pp. 444-447.
 S. C. Terry, J. Blalock, J. M. Rochelle, M. N. Ericson and S. D. Caylor, “Time-Domain Noise Analysis of Lineat Time-Invariant and Linear Time-Variant Systems Using MATLAB and HSPICE,” IEEE Transactions on Nuclear Science, Vol. 52, No. 3, 2005, pp. 1418-1422.