MNSMS  Vol.3 No.1 B , January 2013
The Charge Storage of Doubly Stacked Nanocrystalline-Si based Metal Insulator Semiconductor Memory Structure
ABSTRACT
Doubly stacked nanocrystalline-Si (nc-Si) based metal insulator semiconductor memory structure was fabricated by plasma enhanced chemical vapor deposition. Capacitance-Voltage (C-V) and capacitance-time (C-t) measurements were used to investigate electron tunnel, storage and discharging characteristic. The C-V results show that the flatband voltage increases at first, then decreases and finally increases, exhibiting a clear deep at gate voltage of 9 V. The de-creasing of flatband voltage at moderate programming bias is attributed to the transfer of electrons from the lower nc-Si layer to the upper nc-Si layer. The C-t measurement results show that the charges transfer in the structure strongly de-pends on the hold time and the flatband voltage decreases markedly with increasing the hold time.

Cite this paper
X. Wang, C. Song, Y. Guo, J. Song and R. Huang, "The Charge Storage of Doubly Stacked Nanocrystalline-Si based Metal Insulator Semiconductor Memory Structure," Modeling and Numerical Simulation of Material Science, Vol. 3 No. 1, 2013, pp. 20-22. doi: 10.4236/mnsms.2013.31B006.
References
[1]   S. Tiwari, F. Rama, H. Hanafi, A. Hartstein, E. F. Crabbe and K. Chan, “A silicon nanocrystals based memory,”Appl. Phys. Lett ,Vol. 68, 1996, pp. 1377-1379. doi: 10.1063/1.116085

[2]   T. Feng, H. B. Yu, M. Dicken, J. R. Heath, and H. A. Atwater, “Probing the size and density of silicon nanocrystals in nanocrystal memory device applications,” Appl. Phys. Lett., Vol. 86, 2005, pp. 033103. doi:10.1063/1.1852078

[3]   S. Y. Huang and S. Oda, “Charge storage in nitrided nanocrystalline silicon dots,” Appl. Phys. Lett., Vol. 87, 2005, pp. 173107. doi:10.1063/1.2115069

[4]   M. Dai, K. Chen, X. F. Huang, L. C. Wu and K. J. Chen, “Formation and charging effect of Si nanocrystals in a-SiNx/a-Si/a-SiNx structures,” J. Appl. Phys., Vol. 95, 2004, pp. 640-645. doi:10.1063/1.1633649

[5]   X. Zhou, K. Uchida, and S. Oda, “Current fluctuations in three-dimensionally stacked Si nanocrystals thin films,” Appl. Phys. Lett., Vol. 96, 2010, pp. 092112. doi:10.1063/1.3294329

[6]   T. C. Chang, S. T. Yan, P. T. Liu, H. H. Wu, and S. M. Sze, “Quasisuperlattice storage: A concept of multilevel charge storage,” Appl. Phys. Lett., Vol. 85, 2004, pp. 248-250. doi:10.1063/1.1772873

[7]   T. Z. Lu, M. Alexe, R. Scholz, V. Talelaev, and M. Zacharias, “Multilevel charge storage in silicon nanocrystal multilayers,” Appl. Phys. Lett., Vol. 87, 2005, pp. 202110. doi:10.1063/1.2132083

[8]   T. Z. Lu, M. Alexe, R. Scholz, V. Talalaev, R. J. Zhang, and M. Zacharias, “Si nanocrystal based memories: Effect of the nanocrystal density,” J. Appl. Phys., Vol. 100, 2006, pp. 014310. doi:10.1063/1.2214300

[9]   L. C. Wu, K. J. Chen, J. M. Wang, X. F. Huang, Z. T. Song, and W. L. Liu, “Charge retention enhancement in stack nanocrystalline Si based metal insulator semiconductor memory structure, ” Appl. Phys. Lett., Vol. 89, 2006, pp. 112118. doi:10.1063/1.2352796

[10]   J. Wang, L. Wu, K. Chen, L. Yu, X. Wang, J. Song, and X. Huang, “Charge storage in self-aligned doubly stacked Si nanocrystals in SiNx dielectric,” J. Appl. Phys., Vol. 101, 2007, pp. 014325. doi:10.1063/1.2409280

[11]   L. C. Wu, M. Dai, X. F. Huang, W. Li, and K. J. Chen, “Size-dependent resonant tunneling and storing of electrons in a nanocrystalline silicon floating gate double barrier structure,” J. Vac. Sci. Technol. B, Vol. 22, 2004, pp. 678-681. doi:10.1116/1.1676527

[12]   T. H. Ng, W. K. Chim, and W. K. Choi, “Conductance voltage measurements on germanium nanocrystal memory structures and effect of gate electric field coupling,” Appl. Phys. Lett., Vol. 88, 2006, pp. 113112. doi:10.1063/1.2186738

[13]   A. Sawada, “Internal electric fields of electrolytic solutions induced by space-charge polarization,” J. Appl. Phys., Vol. 100, 2006, pp. 074103. doi:/10.1063/1.2355449

 
 
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