Future Semiconductor Devices for Multi-Valued Logic Circuit Design

Affiliation(s)

Intel Corporation, Hillsboro, USA.

Department of Electrical & Computer Engineering, University of Connecticut, Storrs, USA.

Intel Corporation, Hillsboro, USA.

Department of Electrical & Computer Engineering, University of Connecticut, Storrs, USA.

ABSTRACT

This paper introduces future devices for multi-valued logic implementation. Quantum dot gate field effect transistor (QDGFET) works based on the change in threshold voltage due to stored charge in the quantum dots in the gate region. Quantum dot channel field effect transistor (QDCFET) produces more number of states in their transfer characteristics because of charge flow through the mini-band structure formed by the overlapping energy bands of the neighboring quantum dots in the channel region of the FET. On the other hand spatial wave-function switched field effect transistor (SWSFET) produces more number of states in its transfer characteristic based on the switching of charge carriers from one channel to other channel of the device. In this paper we discuss QDGFET, QDCFET and SWSFET in detail to explore their application in future multi-valued logic circuits.

This paper introduces future devices for multi-valued logic implementation. Quantum dot gate field effect transistor (QDGFET) works based on the change in threshold voltage due to stored charge in the quantum dots in the gate region. Quantum dot channel field effect transistor (QDCFET) produces more number of states in their transfer characteristics because of charge flow through the mini-band structure formed by the overlapping energy bands of the neighboring quantum dots in the channel region of the FET. On the other hand spatial wave-function switched field effect transistor (SWSFET) produces more number of states in its transfer characteristic based on the switching of charge carriers from one channel to other channel of the device. In this paper we discuss QDGFET, QDCFET and SWSFET in detail to explore their application in future multi-valued logic circuits.

Cite this paper

S. Karmakar and F. Jain, "Future Semiconductor Devices for Multi-Valued Logic Circuit Design,"*Materials Sciences and Applications*, Vol. 3 No. 11, 2012, pp. 807-814. doi: 10.4236/msa.2012.311117.

S. Karmakar and F. Jain, "Future Semiconductor Devices for Multi-Valued Logic Circuit Design,"

References

[1] G. E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics, Vol. 38, No. 8, 1965, pp. 114-117.

[2] G. E. Moore, “No Exponential Is Forever: But ‘Forever’ Can Be Delayed!” Solid-State Circuits Conference, IEEE International Digest of Technical Papers, Vol. 1, 2003, pp. 20-23. doi:10.1109/ISSCC.2003.1234194

[3] E. J. Nowak, “Maintaining the Benefits of CMOS Scaling When Scaling Bogs Down,” Journal of Research and Development, Vol. 46, No. 2-3, 2002, pp. 169-180.

[4] T. N. Theis, “Beyond the Silicon Transistor: Personal Observations,” Computing in Science & Engineering, Vol. 5, No. 1, 2003, pp. 25-29.

[5] S. Borkar, “Design Perspectives on 22 nm CMOS and beyond,” Design Automation Conference, San Francisco, 26-31 July 2009, pp. 93-94.

[6] M. Goto, S. Kawanaka, S. Inumiya, N. Kusunoki, M. Saitoh, K. Tatsumura, A. Kinoshita, S. Inaba and Y. Toyoshima, “The Study of Mobility-Tin, Trade-Off in Deeply Scaled High-k/Metal Gate Devices and Scaling Design Guideline for 22 nm-Node Generation,” 2009 Symposium on VLSI Technology, Kyoto, 16-18 June 2009, pp. 214-215.

[7] R. Huang, H. M. Wu, J. F. Kang, D. Y. Xiao, X. L. Shi, X. An, Y. Tian, R. S. Wang, L. L. Zhang, X. Zhang,*et* *al*., “Challenges of 22 nm and beyond CMOS Technology,” Science in China Series F: Information Sciences, Vol. 52, No. 9, 2009, pp. 1491-1533.

[8] S. Thompson,*et* *al*., “A 90 nm Logic Technology Featuring 50 nm Strained Silicon Channel Transistors, 7 Layers of Cu Interconnects, Low k ILD, and 1 μm2 SRAM Cell,” International Electron Devices Meeting Technical Digest, Vol. 6, 2002, pp. 61-64.

[9] K. Mistry,*et* *al*., “A 45 nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-Free Packaging,” International Electron Devices Meeting Technical Digest, Washington DC, 10-12 December 2007, pp. 247-250.

[10] P. Bai,*et* *al*., “A 65 nm Logic Technology Featuring 35 nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57 μm2 SRAM Cell,” International Electron Devices Meeting Technical Digest, San Francisco, 13-15 December 2004, pp. 657-660.

[11] H. K. Lim and J. G. Fossum, “Threshold Voltage of Thin-Film Silicon-on-Insulator (SOI) Mosfet’s,” IEEE Transactions on Electron Devices, Vol. 30, No. 10, 1983, pp. 1244-1251. doi:10.1109/T-ED.1983.21282

[12] J. P. Colinge, “Transconductance of Silicon-on-Insulator Mosfets,” IEEE Electron Device Letters, Vol. EDL-6, 1985, pp. 573-574. doi:10.1109/EDL.1985.26234

[13] L. J. Micheel, A. H. Taddiken and A. C. Seabaugh, “Multiple-Valued Logic Computation Circuits Using Micro and Nanoelectronics Devices,” Proceedings of 23rd IEEE International Symposium on Multiple-Valued Logic, Sacramento, 24-27 May 1993, pp. 164-169.

[14] A. C. Seabaugh, W. R. Frensley, J. N. Randall, M. A. Reed, D. L. Farrington and R. J. Matyi, “Pseudomorphic Bipolar Quantum Resonant-Tunneling Transistor,” IEEE Transaction on Electron Devices, Vol. 36, No. 10, 1989, pp. 2228-2234.

[15] J. Stock, J. Malindretos, K. M. Indlekofer, M. Pottgens, A. Forster and H. Luth, “A Vertical Resonant Tunneling Transistor for Application in Digital Logic Circuits,” IEEE Transaction on Electron Devices, Vol. 48, No. 6, 2001, pp. 1028-1032.

[16] F. Capasso and R. A. Kiehl, “Resonant Tunneling Transistor with Quantum Well Base and High-Energy Injection: A New Negative Differential Resistance Device”, Journal of Applied Physics, Vol. 58, No. 3, 1985, pp. 1366-1368.

[17] H. C. Lin, “Resonant Tunneling Diodes for Multi-Valued Digital Applications,” Proceedings of 24th IEEE International Symposium on Multiple-Valued Logic, Boston, 25 27 May 1994, pp. 188-195.

[18] A. Forster, “Resonant Tunneling Diodes: The Effect of Structural Properties on Their Performance,” Advances in Solid State Physics, Vol. 33, 1993, pp. 37-62.

[19] T. Waho, K. J. Chen and M. Yamamoto, “Resonant Tunneling Diode and HEMT Logic Circuits with Multiple Thresholds and Multi-Level Output,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 2, 1998, pp. 268-274.

[20] H. C. Lin, “Resonant Tunneling Diodes for Multi-Valued Digital Applications,” Proceedings of 24th IEEE International Symposium on Multiple-Valued Logic, Boston, 25 27 May 1994, pp. 188-195.

[21] P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun and G. I. Haddad, “Digital Circuit Applications of Resonant Tunneling Diodes,” Proceedings of IEEE, Vol. 86, No. 4, 1998, pp. 664-686. doi:10.1109/5.663544

[22] J. P. A. van der Wagt, H. Tang, T. P. E. Broekaert, A. C. Seabaugh and Y.-C. Kao, “Multibit Resonant Tunneling Diode SRAM Cell Based on Slew-Rate Addressing,” IEEE Transactions on Electron Devices, Vol. 46, No. 1, 1999, p. 5562. doi:10.1109/16.737441

[23] T. Waho, “Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits,” Proceedings of 25th IEEE International Symposium on Multiple-Valued Logic, 1995, pp.130-138.

[24] W. L. Chen, G. O. Mums, L. Davis, P. K. Bhattacharya and G. I. Haddad, “The Growth of Resonant Tunneling Hot Electron Transistors Using Chemical Beam Epitaxy,” The 4th International Conference in Chemical Beam Epitaxy, Section S-7, Nara, 21-23 July 1993.

[25] T. Futatsugi, Y. Yamaguchi, K. Ishii, K. Imamura, S. Muto, N. Yokoyama and A. Shibatomi, “A Resonant Tun neling Bipolar Transistor (RBT): A Proposal and Demon stration for New Functional Device with High Current Gains,” International Electron Devices Meeting Techni cal Digest, Washington DC, 7-10 December 1986, p. 286.

[26] A. C. Seabaugh, W. R. Frensley, Y. C. Kao, J. N. Randall and M. A. Reed, “Quantum-Well Resonant Tunneling Transistors,” The Proceedings of the 1989 IEEE Conference, Ithaca, 1989, p. 255.

[27] S. Karmakar, M. Gogna, E. Suarez, F. Alamoody, E. Heller, J. chandy and F. Jain, “3-State Behavior of Quantum Dot Gate FETs with Lattice Matched Insulator,” Proceedings of 2009 Nanoelectronic Devices for Defense and Security, Fort Lauderdale, 28 September-2 October 2009.

[28] S. Karmakar, J. A. Chandy and F. C. Jain, “Application of 25 nm Quantum Dot Gate FETs to the Design of ADC and DAC Circuits,” International Journal of High Speed Electronics and Systems, Vol. 20, No. 3, 2011, p. 653.

[29] S. Karmakar, A. P. Suresh, J. A. Chandy and F. C. Jain, “Design of ADCs and DACs Using 3-State Quantum DOT Gate FETs,” Proceedings of International Semi conductor Device Research Symposium, College Park, 9-11 December 2009.

[30] S. Karmakar, E. Suarez and F. Jain, “Quantum Dot Gate Three State FETs Using ZnS-ZnMgS Lattice-Matched Gate Insulator on Silicon,” Journal of Electronic Materi als, Vol. 40, No. 8, 2011, pp. 1749-1756.

[31] F. Jain, S. Karmakar, R. A. Croce Jr., M. Gogna, E. Suarez, J. Chandy and E. Heller, “Multi-State Quantum Dot Channel (QDC) Field-Effect Transistors (FETs): A New Paradigm in Circuit Design,” 2011 Nanoelectronic Devices for Security Conference, Brooklyn, 29 August-1 September 2011.

[32] F. Jain, S. Karmakar, P.-Y. Chan, E. Suarez, M. Gogna, J. Chandy and E. Heller, “Quantum Dot Channel (QDC) Field-Effect Transistors (FETs) Using II-VI Barrier Lay ers,” Journal of Electronic Materials, Vol. 41, No. 10, 2012, pp. 2775-2784. doi:10.1007/s11664-012-2161-z

[33] F. C. Jain, B. Miller, E. Suarez, P.-Y. Chan, S. Karmakar, F. Al-Amoody, J. Chandy and E. Heller, “Spatial Wave function Switched (SWS) InGaAs FETs with II-VI Gate Insulators,” Journal of Electronic Materials, Vol. 40, No. 8, 2011, pp. 1717-1726. doi:10.1007/s11664-011-1667-0

[34] S. Karmakar, F. C. Jain, J. A. Chandy and E. Heller, “Circuit Model of SWSFET to Implement Multi-Valued Logic,” 21st CMOC Symposium, University of Connecti cut, Storrs, 9 April 2012.

[35] S. Karmakar, J. A. Chandy and F. C. Jain, “Implementation of Unipolar Inverter Based on Spatial Wave-Function Switched (SWS) FET,” IEEE Lester Eastman Conference on High Performance Devices, Brown University, Providence, 7-9 August 2012.

[1] G. E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics, Vol. 38, No. 8, 1965, pp. 114-117.

[2] G. E. Moore, “No Exponential Is Forever: But ‘Forever’ Can Be Delayed!” Solid-State Circuits Conference, IEEE International Digest of Technical Papers, Vol. 1, 2003, pp. 20-23. doi:10.1109/ISSCC.2003.1234194

[3] E. J. Nowak, “Maintaining the Benefits of CMOS Scaling When Scaling Bogs Down,” Journal of Research and Development, Vol. 46, No. 2-3, 2002, pp. 169-180.

[4] T. N. Theis, “Beyond the Silicon Transistor: Personal Observations,” Computing in Science & Engineering, Vol. 5, No. 1, 2003, pp. 25-29.

[5] S. Borkar, “Design Perspectives on 22 nm CMOS and beyond,” Design Automation Conference, San Francisco, 26-31 July 2009, pp. 93-94.

[6] M. Goto, S. Kawanaka, S. Inumiya, N. Kusunoki, M. Saitoh, K. Tatsumura, A. Kinoshita, S. Inaba and Y. Toyoshima, “The Study of Mobility-Tin, Trade-Off in Deeply Scaled High-k/Metal Gate Devices and Scaling Design Guideline for 22 nm-Node Generation,” 2009 Symposium on VLSI Technology, Kyoto, 16-18 June 2009, pp. 214-215.

[7] R. Huang, H. M. Wu, J. F. Kang, D. Y. Xiao, X. L. Shi, X. An, Y. Tian, R. S. Wang, L. L. Zhang, X. Zhang,

[8] S. Thompson,

[9] K. Mistry,

[10] P. Bai,

[11] H. K. Lim and J. G. Fossum, “Threshold Voltage of Thin-Film Silicon-on-Insulator (SOI) Mosfet’s,” IEEE Transactions on Electron Devices, Vol. 30, No. 10, 1983, pp. 1244-1251. doi:10.1109/T-ED.1983.21282

[12] J. P. Colinge, “Transconductance of Silicon-on-Insulator Mosfets,” IEEE Electron Device Letters, Vol. EDL-6, 1985, pp. 573-574. doi:10.1109/EDL.1985.26234

[13] L. J. Micheel, A. H. Taddiken and A. C. Seabaugh, “Multiple-Valued Logic Computation Circuits Using Micro and Nanoelectronics Devices,” Proceedings of 23rd IEEE International Symposium on Multiple-Valued Logic, Sacramento, 24-27 May 1993, pp. 164-169.

[14] A. C. Seabaugh, W. R. Frensley, J. N. Randall, M. A. Reed, D. L. Farrington and R. J. Matyi, “Pseudomorphic Bipolar Quantum Resonant-Tunneling Transistor,” IEEE Transaction on Electron Devices, Vol. 36, No. 10, 1989, pp. 2228-2234.

[15] J. Stock, J. Malindretos, K. M. Indlekofer, M. Pottgens, A. Forster and H. Luth, “A Vertical Resonant Tunneling Transistor for Application in Digital Logic Circuits,” IEEE Transaction on Electron Devices, Vol. 48, No. 6, 2001, pp. 1028-1032.

[16] F. Capasso and R. A. Kiehl, “Resonant Tunneling Transistor with Quantum Well Base and High-Energy Injection: A New Negative Differential Resistance Device”, Journal of Applied Physics, Vol. 58, No. 3, 1985, pp. 1366-1368.

[17] H. C. Lin, “Resonant Tunneling Diodes for Multi-Valued Digital Applications,” Proceedings of 24th IEEE International Symposium on Multiple-Valued Logic, Boston, 25 27 May 1994, pp. 188-195.

[18] A. Forster, “Resonant Tunneling Diodes: The Effect of Structural Properties on Their Performance,” Advances in Solid State Physics, Vol. 33, 1993, pp. 37-62.

[19] T. Waho, K. J. Chen and M. Yamamoto, “Resonant Tunneling Diode and HEMT Logic Circuits with Multiple Thresholds and Multi-Level Output,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 2, 1998, pp. 268-274.

[20] H. C. Lin, “Resonant Tunneling Diodes for Multi-Valued Digital Applications,” Proceedings of 24th IEEE International Symposium on Multiple-Valued Logic, Boston, 25 27 May 1994, pp. 188-195.

[21] P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun and G. I. Haddad, “Digital Circuit Applications of Resonant Tunneling Diodes,” Proceedings of IEEE, Vol. 86, No. 4, 1998, pp. 664-686. doi:10.1109/5.663544

[22] J. P. A. van der Wagt, H. Tang, T. P. E. Broekaert, A. C. Seabaugh and Y.-C. Kao, “Multibit Resonant Tunneling Diode SRAM Cell Based on Slew-Rate Addressing,” IEEE Transactions on Electron Devices, Vol. 46, No. 1, 1999, p. 5562. doi:10.1109/16.737441

[23] T. Waho, “Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits,” Proceedings of 25th IEEE International Symposium on Multiple-Valued Logic, 1995, pp.130-138.

[24] W. L. Chen, G. O. Mums, L. Davis, P. K. Bhattacharya and G. I. Haddad, “The Growth of Resonant Tunneling Hot Electron Transistors Using Chemical Beam Epitaxy,” The 4th International Conference in Chemical Beam Epitaxy, Section S-7, Nara, 21-23 July 1993.

[25] T. Futatsugi, Y. Yamaguchi, K. Ishii, K. Imamura, S. Muto, N. Yokoyama and A. Shibatomi, “A Resonant Tun neling Bipolar Transistor (RBT): A Proposal and Demon stration for New Functional Device with High Current Gains,” International Electron Devices Meeting Techni cal Digest, Washington DC, 7-10 December 1986, p. 286.

[26] A. C. Seabaugh, W. R. Frensley, Y. C. Kao, J. N. Randall and M. A. Reed, “Quantum-Well Resonant Tunneling Transistors,” The Proceedings of the 1989 IEEE Conference, Ithaca, 1989, p. 255.

[27] S. Karmakar, M. Gogna, E. Suarez, F. Alamoody, E. Heller, J. chandy and F. Jain, “3-State Behavior of Quantum Dot Gate FETs with Lattice Matched Insulator,” Proceedings of 2009 Nanoelectronic Devices for Defense and Security, Fort Lauderdale, 28 September-2 October 2009.

[28] S. Karmakar, J. A. Chandy and F. C. Jain, “Application of 25 nm Quantum Dot Gate FETs to the Design of ADC and DAC Circuits,” International Journal of High Speed Electronics and Systems, Vol. 20, No. 3, 2011, p. 653.

[29] S. Karmakar, A. P. Suresh, J. A. Chandy and F. C. Jain, “Design of ADCs and DACs Using 3-State Quantum DOT Gate FETs,” Proceedings of International Semi conductor Device Research Symposium, College Park, 9-11 December 2009.

[30] S. Karmakar, E. Suarez and F. Jain, “Quantum Dot Gate Three State FETs Using ZnS-ZnMgS Lattice-Matched Gate Insulator on Silicon,” Journal of Electronic Materi als, Vol. 40, No. 8, 2011, pp. 1749-1756.

[31] F. Jain, S. Karmakar, R. A. Croce Jr., M. Gogna, E. Suarez, J. Chandy and E. Heller, “Multi-State Quantum Dot Channel (QDC) Field-Effect Transistors (FETs): A New Paradigm in Circuit Design,” 2011 Nanoelectronic Devices for Security Conference, Brooklyn, 29 August-1 September 2011.

[32] F. Jain, S. Karmakar, P.-Y. Chan, E. Suarez, M. Gogna, J. Chandy and E. Heller, “Quantum Dot Channel (QDC) Field-Effect Transistors (FETs) Using II-VI Barrier Lay ers,” Journal of Electronic Materials, Vol. 41, No. 10, 2012, pp. 2775-2784. doi:10.1007/s11664-012-2161-z

[33] F. C. Jain, B. Miller, E. Suarez, P.-Y. Chan, S. Karmakar, F. Al-Amoody, J. Chandy and E. Heller, “Spatial Wave function Switched (SWS) InGaAs FETs with II-VI Gate Insulators,” Journal of Electronic Materials, Vol. 40, No. 8, 2011, pp. 1717-1726. doi:10.1007/s11664-011-1667-0

[34] S. Karmakar, F. C. Jain, J. A. Chandy and E. Heller, “Circuit Model of SWSFET to Implement Multi-Valued Logic,” 21st CMOC Symposium, University of Connecti cut, Storrs, 9 April 2012.

[35] S. Karmakar, J. A. Chandy and F. C. Jain, “Implementation of Unipolar Inverter Based on Spatial Wave-Function Switched (SWS) FET,” IEEE Lester Eastman Conference on High Performance Devices, Brown University, Providence, 7-9 August 2012.