ENG  Vol.4 No.8 , August 2012
Fast CR-SRAM Using New Charge-Recycling Scheme
Abstract
In this paper, a CR-SRAM using new charge recycling scheme is described, novel bit-line pre-charge voltage distribution is proposed. The SRAM pre-charge voltage level is designed by logarithm instead of linear. The new design leads to improvement in speed compared to the original CR-SRAM. Simulation results show that the new CR-SRAM using novel pre-charge voltage distribution scheme reduced the write access time by 34% with 9% power dissipation penalty.

Cite this paper
L. Li, X. Chen and X. Wang, "Fast CR-SRAM Using New Charge-Recycling Scheme," Engineering, Vol. 4 No. 8, 2012, pp. 493-495. doi: 10.4236/eng.2012.48064.
References

[1]   K. Keejong, H. Mahmoodi and K. Roy, “A Low-Power SRAM Using Bit-Line Charge-Recycling,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 2, 2008, pp. 446-459. doi:10.1109/JSSC.2007.914294

[2]   B.-D. Yang, “A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations,” IEEE Journal of Solid-State Circuits, Vol. 45, No. 10, 2010, pp. 2173-2183. doi:10.1109/JSSC.2010.2063950

[3]   H. Yamauchi, H. Akamatsu and T. Fujita, “An Asymtotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI’s,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 4, 1995, pp. 423-431. doi:10.1109/4.375962

[4]   B. D. Yang and L. S. Kim, “A Low Power Charge-Recycling ROM Architecture,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 4, 2003, pp. 590-600.

[5]   M. Yamaoka, N. Maeda, Y. Shinozaki, K. Nii, S. Shimada, K. Yanagi-sawa and T. Kawahara, “90-nm Process-Variation Adaptive Embedded SRAM Modules with Power-Line-Floating Write Technique,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 3, 2006, pp. 705-711. doi:10.1109/JSSC.2006.869786

 
 
Top