WET  Vol.3 No.3 , July 2012
Design of Low Power CMOS LNA with Current-Reused and Notch Filter Topology for DS-UWB Application
Abstract
This paper presents the design of a low power LNA with second stage that uses a notch filter for DS-UWB application. The LNA employs a current reuse structure to reduce the power consumption and an active second order notch filter to produce band rejection in the 5 - 6 GHz frequency band. The input reflection coefficient S11 and output reflection S22 are both less than –10 dB. The maximum power gain S21 is 15 dB while the maximum rejection ratio is over –10 dB at 4.8 GHz. The minimum noise figure is 5 dB. The input referred third-order intercept point (IIP3) is –7 dBm at 6 GHz. The power consumption is 6.4 mW from a 1-V power supply.

Cite this paper
M. Hsu, J. Du and W. Chiu, "Design of Low Power CMOS LNA with Current-Reused and Notch Filter Topology for DS-UWB Application," Wireless Engineering and Technology, Vol. 3 No. 3, 2012, pp. 167-174. doi: 10.4236/wet.2012.33024.
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