Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration

Author(s)
Hiroshi Makino^{*},
Naoya Okada,
Tetsuya Matsumura,
Koji Nii,
Tsutomu Yoshimura,
Shuhei Iwade,
Yoshio Matsuda

Affiliation(s)

Faculty of Information Science and Technology, Osaka Institute of Technology, Hirakata, Japan.

Graduate School of Natural Science, Kanazawa University, Kanazawa, Japan.

SoC Software Platform Division, Renesas Electronics Corporation, Itami, Japan.

Design Platform Development Division, Renesas Electronics Corporation, Kodaira, Japan.

Faculty of Engineering, Osaka Institute of Technology, Osaka, Japan.

Faculty of Information Science and Technology, Osaka Institute of Technology, Hirakata, Japan.

Graduate School of Natural Science, Kanazawa University, Kanazawa, Japan.

SoC Software Platform Division, Renesas Electronics Corporation, Itami, Japan.

Design Platform Development Division, Renesas Electronics Corporation, Kodaira, Japan.

Faculty of Engineering, Osaka Institute of Technology, Osaka, Japan.

ABSTRACT

An accelerated evaluation method for the SRAM cell write margin is proposed using the conventional Write Noise Margin (WNM) definition based on the “butterfly curve”. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is chosen in order to make the access transistor operate in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The WNM shift amount is determined from the measured WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. Together with the maximum likelihood method, a normal distribution of the AWNM drastically improves development efficiency because the write failure probability can be estimated from a small number of samples. The effectiveness of the proposed method is verified using the Monte Carlo simulation.

An accelerated evaluation method for the SRAM cell write margin is proposed using the conventional Write Noise Margin (WNM) definition based on the “butterfly curve”. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is chosen in order to make the access transistor operate in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The WNM shift amount is determined from the measured WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. Together with the maximum likelihood method, a normal distribution of the AWNM drastically improves development efficiency because the write failure probability can be estimated from a small number of samples. The effectiveness of the proposed method is verified using the Monte Carlo simulation.

Cite this paper

H. Makino, N. Okada, T. Matsumura, K. Nii, T. Yoshimura, S. Iwade and Y. Matsuda, "Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration,"*Circuits and Systems*, Vol. 3 No. 3, 2012, pp. 242-251. doi: 10.4236/cs.2012.33034.

H. Makino, N. Okada, T. Matsumura, K. Nii, T. Yoshimura, S. Iwade and Y. Matsuda, "Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration,"

References

[1] M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching Properties of MOS Transistors,” IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, 1989, pp. 1433-1440. doi:10.1109/JSSC.1989.572629

[2] P. A. Stolk, F. P. Widdershoven and D. B. M. Klaassen, “Modeling Statistical Dopant Fluctuations in MOS Transistors,” IEEE Transactions on Electron Devices, Vol. 45, No. 9, 1998, pp. 1960-1971. doi:10.1109/16.711362

[3] O. Hirabayashi, A. Kawasumi, A. Suzuki, Y. Takeyama, K. Kushida, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, T. Nakazato, Y. Shizuki, N. Kushiyama and T. Yabe, “A Process-Variation-Tolerant Dual-Power-Supply SRAM with 0.179 um2 Cell in 40 nm CMOS Using Level Programmable Wordline Driver,” ISSCC Digg Technology Papers, 2009, pp. 458-459.

[4] A. Bhavnagarwala, S. Kosonocky, C. Radens, K. Stawiasz, R. Mann, Q. Ye and K. Chin, “Fluctuation Limits & Scaling Opportunities for CMOS SRAM Cells,” ISSCC Digg Technology Papers, 2005, pp. 659-662.

[5] K. Takeda, H. Ikeda, Y. Hagihara, M. Nomura and H. Kobatake, “Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit,” IEEE ISSCC, Digest of Technology Papers, 2006, pp. 630-631.

[6] N. Gierczynski, B. Borot, N. Planes and H. Brut, “A New Combined Methodology for Write-Margin Extraction of Advanced SRAM,” IEEE International Conferences on Microelectronic Test Structure, 19-22 March 2007, pp. 97100. doi:10.1109/ICMTS.2007.374463

[7] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng and M. Bohr, “A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 1, 2006, pp. 146-151. doi:10.1109/JSSC.2005.859025

[8] C. Wann, R. Wong, D. Frank, R. Mann, S.-B. Ko, P. Croce, D. Lea, D. Hoyniak, Y.-M. Lee, J. Toomey, M. Weybright and J. Sudijono, “SRAM Cell Design for Stability Methodology,” 2005 IEEE VLSI-TSA International Symposium on VLSI Technology, April 2005, pp. 21-22.

[9] E. Grossar, M. Stucchi, K. Maex and W. Dehaene, “Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 11, 2006, pp. 2577-2588. doi:10.1109/JSSC.2006.883344

[10] H. Makino, S. Nakata, H. Suzuki, S. Mutoh, M. Miyama, T. Yoshimura, S. Iwade and Y. Matsuda, “Reexamination of SRAM Cell Write Margin Definitions in View of Predicting Distribution,” Transactions on Circuits and Systems II: Brief Express, Vol. 58, No. 4, 2011, pp. 230-234.

[11] Visit, “45 nm PTM HP Model: V2.1.” http://www.eas.asu.edu/~ptm/

[1] M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching Properties of MOS Transistors,” IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, 1989, pp. 1433-1440. doi:10.1109/JSSC.1989.572629

[2] P. A. Stolk, F. P. Widdershoven and D. B. M. Klaassen, “Modeling Statistical Dopant Fluctuations in MOS Transistors,” IEEE Transactions on Electron Devices, Vol. 45, No. 9, 1998, pp. 1960-1971. doi:10.1109/16.711362

[3] O. Hirabayashi, A. Kawasumi, A. Suzuki, Y. Takeyama, K. Kushida, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, T. Nakazato, Y. Shizuki, N. Kushiyama and T. Yabe, “A Process-Variation-Tolerant Dual-Power-Supply SRAM with 0.179 um2 Cell in 40 nm CMOS Using Level Programmable Wordline Driver,” ISSCC Digg Technology Papers, 2009, pp. 458-459.

[4] A. Bhavnagarwala, S. Kosonocky, C. Radens, K. Stawiasz, R. Mann, Q. Ye and K. Chin, “Fluctuation Limits & Scaling Opportunities for CMOS SRAM Cells,” ISSCC Digg Technology Papers, 2005, pp. 659-662.

[5] K. Takeda, H. Ikeda, Y. Hagihara, M. Nomura and H. Kobatake, “Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit,” IEEE ISSCC, Digest of Technology Papers, 2006, pp. 630-631.

[6] N. Gierczynski, B. Borot, N. Planes and H. Brut, “A New Combined Methodology for Write-Margin Extraction of Advanced SRAM,” IEEE International Conferences on Microelectronic Test Structure, 19-22 March 2007, pp. 97100. doi:10.1109/ICMTS.2007.374463

[7] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng and M. Bohr, “A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 1, 2006, pp. 146-151. doi:10.1109/JSSC.2005.859025

[8] C. Wann, R. Wong, D. Frank, R. Mann, S.-B. Ko, P. Croce, D. Lea, D. Hoyniak, Y.-M. Lee, J. Toomey, M. Weybright and J. Sudijono, “SRAM Cell Design for Stability Methodology,” 2005 IEEE VLSI-TSA International Symposium on VLSI Technology, April 2005, pp. 21-22.

[9] E. Grossar, M. Stucchi, K. Maex and W. Dehaene, “Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 11, 2006, pp. 2577-2588. doi:10.1109/JSSC.2006.883344

[10] H. Makino, S. Nakata, H. Suzuki, S. Mutoh, M. Miyama, T. Yoshimura, S. Iwade and Y. Matsuda, “Reexamination of SRAM Cell Write Margin Definitions in View of Predicting Distribution,” Transactions on Circuits and Systems II: Brief Express, Vol. 58, No. 4, 2011, pp. 230-234.

[11] Visit, “45 nm PTM HP Model: V2.1.” http://www.eas.asu.edu/~ptm/