N. S. Kim and T. Mudge, “The Microarchitecture of a Low Power Register File,” Proceedings of the 2003 International Symposium on Low Power Electronics and Design, Seoul, 25-27 August 2003, pp. 384-389.
 R. Balasubramonian, S. Dwarkadas and D. H. Albonesi, “Reducing the Complexity of the Register File in Dynamic Superscalar Processors,” Proceedings of the 34th annual ACM/IEEE International Symposium on Microarchitecture, Austin, 1-5 December 2001, pp. 237-248.
 Y. Tanaka and H. Ando, “Reducing Register File Size through Instruction Pre-Execution Enhanced by Value Prediction,” Proceedings of the 2009 IEEE International Conference on Computer Design, Nagoya, 4-7 October 2009, pp. 238-245. doi:10.1109/ICCD.2009.5413149
 S. Rixner, W. J. Dally, B. Khailany, P. Mattson, U. J. Kapasi and J. D. Owens, “Register Organization for Media Processing,” Proceedings of the 6th International Symposium on High Performance Computer Architecture, Stanford, January 2000, pp. 375-386.
 K. M. B Ahin, P. Patra and F. N. Najm, “ESTIMA: An Architectural-Level Power Estimator for Multi-Ported Pipelined Register Files,” Proceedings of 2003 International Symposium on Low Power Electronics and Design, Hillsboro, 25-27 August 2003, pp. 294-297.
 N. Kahraman and T. Yildirim, “Technology Independent Circuit Sizing for Standard Cell Based Design Using Neural Networks,” Digital Signal Processing, Vol. 19, No. 4, 2009, pp. 708-714. doi:10.1016/j.dsp.2008.11.009
 F. Djeffal, M. Chahdi, A. Benhaya and M. L. Hafiane, “An Approach Based on Neural Computation to Simulate the Nanoscale CMOS Circuits: Application to the Simulation of CMOS Inverter,” Solid-State Electronics, Vol. 51, No. 1, 2007, pp. 48-56. doi:10.1016/j.sse.2006.12.004
 P. Kalpana and K. Gunavathi, “Wavelet Based Fault Detection in Analog VLSI Circuits Using Neural Networks,” Applied Soft Computing, Vol. 8, No. 4, 2008, pp. 15921598. doi:10.1016/j.asoc.2007.10.023
 A. Suissa, O. Romain, J. Denoulet, K. Hachicha and P. Garda, “Empirical Method Based on Neural Networks for Analog Power Modeling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 5, 2010, pp. 839-844. doi:10.1109/TCAD.2010.2043759
 P. Raghavan, A. Lambrechts and M. Jayapala, F. Catthoor and D. Verkest, “EMPIRE: Empirical Power/Area/ Timing Models for Register Files,” Microprocessors and Microsystems, Vol. 33, 2009, pp. 295-300. doi:10.1016/j.micpro.2009.02.009
 J. A. Abdalla and R. A. Hawileh, “Modeling and Simulation of Low-Cycle Fatigue Life of Steel Reinforcing Bars Using Artificial Neural Network,” Journal of the Franklin Institute, Vol. 348, No. 7, 2011, pp. 1393-1403. doi:10.1016/j.jfranklin.2010.04.005