Back
 CS  Vol.3 No.3 , July 2012
Area and Timing Estimation in Register Files Using Neural Networks
Abstract: The increase in issue width and instructions window size in modern processors demand an increase in the size of the register files, as well as an increase in the number of ports. Bigger register files implies an increase in power consumed by these units as well as longer access delays. Models that assist in estimating the size of the register file, and its timing early in the design cycle are critical to the time-budget allocated to a processor design and to its performance. In this work, we discuss a Radial Base Function (RBF) Artificial Neural Network (ANN) model for the prediction of time and area for standard cell register files designed using optimized Synopsys Design Ware components and an UMC130 nm library. The ANN model predictions were compared against experimental results (obtained using detailed simulation) and a nonlinear regression-based model, and it is observed that the ANN model is very accurate and outperformed the non-linear model in several statistical parameters. Using the trained ANN model, a parametric study was carried out to study the effect of the number of words in the file (D), the number of bit in one word (W) and the total number of Read and Write ports (P) on the latency and area of standard cell register files.
Cite this paper: A. Sagahyroon and J. Abdalla, "Area and Timing Estimation in Register Files Using Neural Networks," Circuits and Systems, Vol. 3 No. 3, 2012, pp. 269-277. doi: 10.4236/cs.2012.33037.
References

[1]   R. Preston, et al., “Design of an 8-Wide Superscalar RISC Microprocessor with Simultaneous Multithreading,” SolidState Circuits Conference, Vol. 1, 7 February 2002, pp. 334-472.

[2]   N. S. Kim and T. Mudge, “The Microarchitecture of a Low Power Register File,” Proceedings of the 2003 International Symposium on Low Power Electronics and Design, Seoul, 25-27 August 2003, pp. 384-389.

[3]   R. Balasubramonian, S. Dwarkadas and D. H. Albonesi, “Reducing the Complexity of the Register File in Dynamic Superscalar Processors,” Proceedings of the 34th annual ACM/IEEE International Symposium on Microarchitecture, Austin, 1-5 December 2001, pp. 237-248.

[4]   Y. Tanaka and H. Ando, “Reducing Register File Size through Instruction Pre-Execution Enhanced by Value Prediction,” Proceedings of the 2009 IEEE International Conference on Computer Design, Nagoya, 4-7 October 2009, pp. 238-245. doi:10.1109/ICCD.2009.5413149

[5]   S. Rixner, W. J. Dally, B. Khailany, P. Mattson, U. J. Kapasi and J. D. Owens, “Register Organization for Media Processing,” Proceedings of the 6th International Symposium on High Performance Computer Architecture, Stanford, January 2000, pp. 375-386.

[6]   J. Tseng and K. Asanovic, “Energy Efficient Register Access,” Proceedings of the 13th Symposium on Integrated Circuits and Systems Design, Cambridge, 2000, pp. 377-382.

[7]   K. M. B Ahin, P. Patra and F. N. Najm, “ESTIMA: An Architectural-Level Power Estimator for Multi-Ported Pipelined Register Files,” Proceedings of 2003 International Symposium on Low Power Electronics and Design, Hillsboro, 25-27 August 2003, pp. 294-297.

[8]   N. Kahraman and T. Yildirim, “Technology Independent Circuit Sizing for Standard Cell Based Design Using Neural Networks,” Digital Signal Processing, Vol. 19, No. 4, 2009, pp. 708-714. doi:10.1016/j.dsp.2008.11.009

[9]   F. Djeffal, M. Chahdi, A. Benhaya and M. L. Hafiane, “An Approach Based on Neural Computation to Simulate the Nanoscale CMOS Circuits: Application to the Simulation of CMOS Inverter,” Solid-State Electronics, Vol. 51, No. 1, 2007, pp. 48-56. doi:10.1016/j.sse.2006.12.004

[10]   P. Kalpana and K. Gunavathi, “Wavelet Based Fault Detection in Analog VLSI Circuits Using Neural Networks,” Applied Soft Computing, Vol. 8, No. 4, 2008, pp. 15921598. doi:10.1016/j.asoc.2007.10.023

[11]   A. Suissa, O. Romain, J. Denoulet, K. Hachicha and P. Garda, “Empirical Method Based on Neural Networks for Analog Power Modeling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 5, 2010, pp. 839-844. doi:10.1109/TCAD.2010.2043759

[12]   P. Raghavan, A. Lambrechts and M. Jayapala, F. Catthoor and D. Verkest, “EMPIRE: Empirical Power/Area/ Timing Models for Register Files,” Microprocessors and Microsystems, Vol. 33, 2009, pp. 295-300. doi:10.1016/j.micpro.2009.02.009

[13]   S. Haykin, “Neural Networks: A Comprehensive Foundation,” 2nd Edition, Prentice-Hall, Upper Saddle River, 1999.

[14]   J. A. Abdalla and R. A. Hawileh, “Modeling and Simulation of Low-Cycle Fatigue Life of Steel Reinforcing Bars Using Artificial Neural Network,” Journal of the Franklin Institute, Vol. 348, No. 7, 2011, pp. 1393-1403. doi:10.1016/j.jfranklin.2010.04.005

 
 
Top