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 CN  Vol.4 No.2 , May 2012
Study of Modeling for Scalable and Monitorable Network on Chip
Abstract: The performance of multiple processor based on Network on Chip (NoC) is limited to the communication efficiency of network. It is difficult to be optimized of routing and arbitration algorithm and be assessed of performance in the beginning of design because of its complex test cases. This paper constructs a scalable and monitored system level model with SystemC for NoC with Packet Connected Circuit (PCC) protocol. The overall performance and transfer details can be evaluated particularly by running the model, and the statistical basis can also be provided to the optimization of designing NoC.
Cite this paper: G. Du, Y. Zhu, C. Zhang and Y. Song, "Study of Modeling for Scalable and Monitorable Network on Chip," Communications and Network, Vol. 4 No. 2, 2012, pp. 183-187. doi: 10.4236/cn.2012.42022.
References

[1]   J. Bhasker, “A SystemC Primer,” 2nd Edition, Star Galaxy Publishing, Allentown, 2002.

[2]   D. Wiklund, “Development and Performance Evaluation of Networks on Chip,” Link?ping University, Linkoping, 2005.

[3]   D. Wiklund and D. Liu, “SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems,” 2003. http://www.da.isy.liu.se/pubs/danwi/danwi-ipdps2003.pdf

[4]   W. Wang, “Design and Performance Analysis on a NoC Router,” 2008.

[5]   H. H. Wen, “Research on the Configurable and MoniTored NoC Prototype Platform,” 2010. http://www.it-paper.com/research-on-the-configurable-and-monitored-noc-prototype-platform.html

 
 
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