ABSTRACT Adaptive noise data filtering in real-time requires dedicated hardware to meet demanding time requirements. Both DSP processors and FPGAs were studied with respect to their performance in power consumption, hardware architecture, and speed for real time applications. For testing purposes, real time adaptive noise filters have been implemented and simulated on two different platforms, Motorola DSP56303 EVM and Xilinx Spartan III boards. This study has shown that in high speed applications, FPGAs are advantageous over DSPs with respect of their speed and noise reduction because of their parallel architecture. FPGAs can handle more processes at the same time when compared to DSPs, while the later can only handle a limited number of parallel instructions at a time. The speed in both processors impacts the noise reduction in real time. As the DSP core gets slower, the noise removal in real time gets harder to achieve. With respect to power, DSPs are advantageous over FPGAs. FPGAs have reconfigurable gate structure which consumes more power. In case of DSPs, the hardware has been already configured, which requires less power consumption? FPGAs are built for general purposes, and their silicon area in the core is bigger than that of DSPs. This is another factor that affects power consumption. As a result, in high frequency applications, FPGAs are advantageous as compared to DSPs. In low frequency applications, DSPs and FPGAs both satisfy the requirements for noise cancelling. For low frequency applications, DSPs are advantageous in their power consumption and applications for the battery power devices. Software utilizing Matlab, VHDL code run on Xilinix system, and assembly running on Motorola development systems, have been used for the demonstration of this study.
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nullA. Hayim, M. Knieser and M. Rizkalla, "DSPs/FPGAs Comparative Study for Power Consumption, Noise Cancellation, and Real Time High Speed Applications," Journal of Software Engineering and Applications, Vol. 3 No. 4, 2010, pp. 391-403. doi: 10.4236/jsea.2010.34044.
 A. Di Stefano, A. Scaglione and C. Giaconia, “Efficient FPGA Implementation of an Adaptive Noise Canceller,” Proceedings Seventh International Workshop on Com-puter Architecture for Machine Perception, Palermo, 2005, pp. 87-89.
M. El-Sharkawy, “Digital Signal Processing Applications with Motorola's DSP56002 Processor,” Prentice Hall, Upper Saddle River, 1996.
K. Joonwan and A. D. Poularikas, “Performance of Noise Canceller Using Adjusted Step Size LMS Algorithm,” Proceedings of the Thirty-Fourth Southeastern Symposium on System Theory, Huntsville, 2002, pp. 248-250.
R. M. Mersereau and M. J. T. Smith, “Digital Filtering A Computer Laboratory Textbook,” John Wiley & Sons, Inc., New York, 1994.
J. Proakis and D. Manolakis, “Digital Signal Processing Principles, Algorithms, and Applications,” 4th Edition, Pearson Prentice Hall, Upper Saddle River, 2007.
G. Saxena, S. Ganesan and M. Das, “Real Time Imple-mentation of Adaptive Noise Cancellation,” EIT 2008 IEEE International Conference on Electro/Information Technology, Ames, 2008, pp. 431-436.
K. L. Su, “Analog Filters,” Chapman & Hall, London, 1996.
B. Widrow, J. R. Glover, Jr., J. M. McCool, J. Kaunitz, C. S. Williams, R. H. Hearn, J. R. Zeidler, Eugene Dong, Jr., and R. C. Goodlin, “Adaptive Noise Cancelling: Principles and Applications,” Proceedings of the IEEE, Vol. 63, 1975, pp. 1692-1716.
S. M. Kuo and D. R. Morgan, “Active Noise Control: A Tutorial Review,” Proceedings of the IEEE, Vol. 87, No. 6, June 1999, pp. 943-973.
K. C. Zangi, “A New Two-Sensor Active Noise Cancella-tion Algorithm,” IEEE International Conference on Acoustics, Speech, and Signal Processing, Minneapolis, Vol. 2, 1993, pp. 351-354.
A. V. Oppenheim, E. Weinstein, K. C. Zangi, M. Feder, and D. Gauger, “Single-Sensor Active Noise Cancella-tion,” IEEE Transactions on Speech and Audio Processing, Vol. 2, 1994, pp. 285-290.
T. H. Yeap, D. K. Fenton and P. D. Lefebvre, “Novel Common Mode Noise Cancellation Techniques for xDSL Applications,” Proceedings of the 19th IEEE Instrumen-tation and Measurement Technology Conference, An-chorage, Vol. 2, 2002, pp. 1125-1128.
Xilinx Corp., “Spartan-IIIE 1.8V FPGA Family: Func-tional Description,” November 2002.
B. Dukel, M. E. Rizkalla and P. Salama, “Implementation of Pipelined LMS Adaptive Filter for Low-Power VLSI Applications,” The 45th Midwest Symposium on Circuits and Systems, Tulsa, Vol. 2, 2002, pp. II-533- II-536.
M. Das, “An Improved Adaptive Wiener Filter for De-noising and Signal Detection,” International Associa-tion of Science and Technology for Development, Inter-national Conference on Signal and Image Processing, Honolulu, 2005, pp. 258.
K. Schutz, “Code Verification using RTDX,” MathWorks Matlab Central File Exchange.
S. Haykin, “Adaptive Filter Theory,” Englewood Cliffs, Prentice Hall, Upper Saddle River, 1991.
D. L. Donoho and J. M. Johnstone, “Ideal Spatial Adapta-tion by Wavelet Shrinkage,” Biometrika, Vol. 81, 1 Sep-tember 1994, pp. 425-455.
J. Petrone, “Adaptive Filter Architectures for FPGA Im-plementation,” Master’s Thesis, Department of Electrical and Computer Engineering, Florida State University, Tal- lahassee, 2004.
S. Manikandan and M. Madheswaran, “A New Design of Adaptive Noise Cancellation for Speech Signals Using Grazing Estimation of Signal Method,” International Conference on Intelligent and Advanced Systems, Kuala Lumpur, 2007, pp. 1265-1269.
K. Chang-Min, P. Hyung-Min, K. Taesu, C. Yoon-Kyung and L. Soo-Young, “FPGA Implementation of ICA Algo-rithm for Blind Signal Separation and Adaptive Noise Canceling,” IEEE Transactions on Neural Networks, Vol. 14, 2003, pp. 1038-1046.
S. M. Kay, “Fundamentals of Statistical Signal Processing,” Prentice Hall, Upper Saddle River, 1996.
J.-S. Lee, “Digital Image Enhancement and Noise Filtering by Use of Local Statistics,” IEEE Transactions on Pattern Analysis and Machine Intelligence, Vol. PAMI-2, 1980, pp. 165-168.
Alon Halim, “Real Time Noise Cancellation Field Pro-grammable Gate Arrays,” MSECE Thesis, Purdue Uni-versity, Lafayette, 2009.