ABSTRACT The size and performance of a System LSI depend heavily on the architecture which is chosen. As a result, the architecture design phase is one of the most important steps in the System LSI development process and is critical to the commercial success of a device. In this paper, we propose a C-based variable length and vector pipeline (VVP) architecture design methodology and apply it to the design of the output probability computation circuit for a speech recognition system. VVP processing accelerated by loop optimization, memory access methods, and application-specific cir- cuit design was implemented to calculate the Hidden Markov Model (HMM) output probability at high speed and its performance is evaluated. It is shown that designers can explore a wide range of design choices and generate complex circuits in a short time by using a C-based pipeline architecture design method.
Cite this paper
T. Kambe and N. Araki, "A C-Based Variable Length and Vector Pipeline Architecture Design Methodology and Its Application," Circuits and Systems, Vol. 3 No. 1, 2012, pp. 10-16. doi: 10.4236/cs.2012.31002.
 G. D. Micheli, “Sythesis and Optimization of Digital circuits,” McGraw-Hill, New York, 1994.
 F. Catthoor and H. J. De Man, “Application-Specific Architectural Methodologies for High-Throughput Digital Signal and Image Processing,” IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 38, No. 2, 1990, pp. 339-349. doi:10.1109/29.103069
 S. Kobayashi, K. Mita, Y. Takeuchi and M. Imai, “Design Space Exploration for DSP Applications Using the ASIP Development System PEAS-III,” Proceedings of the Acoustics, Speech, and Signal Processing, Vol. 3, 13-17 May 2002, pp. 3168-3171.
 H. Blume, H. Hubert, H. T. Feldkamper and T. G. Noll. “Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip,” Journal of VLSI Signal Processing Systems, Vol. 40, No. 1, 2005, pp.19-34.
 S. Pasricha and N. Dutt, “COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC,” Proceedings of the Conference on Design, Automation and Test in Europe, 6-10 March 2006, pp. 700-705.
 M. P. Vestias and H. C. Neto, “Co-Synthesis of a Configurable SoC Platform Based on a Network on Chip Architecture,” Asia and South Pacific Conference on Design Automation, Yokohama, 24-27 January 2006, pp. 48-53. doi:10.1109/ASPDAC.2006.1594644
 O. Schliebusch, A. Hoffmann, A. Nohl, G. Braun and H. Meyr, “Architecture Implementation Using the Machine Description Language LISA,” Proceeding of the Asia and South Pacific Design Automation, Bangalore, 7-11 January 2002, pp. 239-244.
 A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt and A. Nicolau, “EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability,” The Proceeding of Design, Automation and Test in Europe Conference and Exhibition, 9-12 March 1999, pp. 485-490. doi:10.1145/307418.307549
 K. Okada, A. Yamada and T. Kambe: “Hardware Algorithm Optimization Using Bach C,” IEICE Transactions on Fundamentals, Vol. E85-A, No. 4, 2002, pp. 835-841.
 T. Kambe, A. Yamada, K. Okada, M. Ohnishi, A. Kay, P. Boca, V. Zammit and T. Nomura, “A C-Based Synthesis System, Bach, and Its Application,” Proceeding of the Asia and South Pacific Design Automation, 30 January-02 February 2001, pp. 151-155.
 T. Kambe, H. Matsuno, Y. Miyazaki and A. Yamada, “C-Based Design of a Real Time Speech Recognition System,” Proceeding of IEEE International Symposium on Circuits and Systems, Island of Kos, 21-24 May 2006, pp. 1751-1755. doi:10.1109/ISCAS.2006.1692944
 K. Jyoko, T. Ohguchi, H. Uetsu, K. Sakai, T. Ohkura and T. Kambe, “C-Based Design of a Particle Tracking System,” Proceeding of the 13th Workshop on Synthesis and System Integration of Mixed Information Technologies, 2006, pp. 92-96.
 H. Cheng, “Vector Pipeling, Chaining and Speed on the IBM 3090 and Cray X-MP,” IEEE Computer, Vol. 22, No. 9, September 1989, pp. 31-42, 44, 46.
 K. Shikano, K. Itoh, T. Kawahara, K. Takeda and M. Yamamoto; “IT TEXT Speech Recognition System,” Ohomu Co., May 2001 (in Japanese).
 T. Anantharaman and B. Bisiani, “A Hardware Accelerator for Speech Recognition Algorithms,” Proceedings of the 13th Annual International Symposium on Computer Architecture, Vol. 14, No. 2, 1986, pp. 216-223.
 S. Chatterjee and P. Agrawal, “Connected Speech Recognition on a Multiple Processor Pipeline,” Proceedings of International Conference on Acoustics, Speech, and Sig- nal Processing, Vol. 2, 23-26 May 1989, pp. 774-777.
 H. Hon, “A Survey of Hardware Architectures Designed for Speech Recognition,” Technical Report CMU-CS-91-169, August 1991.
 S. Kaxiras, G. Narlikar, A. Berenbaum and Z. Hu, “Comparing Power Consumption of an SMT and a CMP DSP for Mobile Phone Workloads,” Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, November 2001, pp. 211-220. doi:10.1145/502217.502254
 B. Mathew, A. Davis and Z. Fang, “A Low-Power Accelerator for the SPHINX 3 Speech Recognition System,” Proceedings of International Conference on Compilers, Architecture and Synthesis for Embedded Systems, 2003, pp. 210-219. doi:10.1145/951710.951739
 J. M. Muller, “Elementary Functions,” Birkhauser, Boston, 1997.