CS  Vol.3 No.1 , January 2012
Novel Threshold-Based Standard-Cell Flash ADC
Abstract: This paper introduces a novel standard-cell flash architecture for implementing analog-to-digital converters (ADC). The proposed ADC consists of several CMOS inverters all having their inputs connected to a common input node. The out-put of the ADC is a thermometer code generated by the inverter outputs. Depending on the relationship between the input signal and a given inverter’s threshold voltage, the output will either be ‘0’ or ‘1’. By having many inverters with different threshold voltages, it is possible to create a 3-bit flash ADC. Even though the system is inherently non-linear, mathematical optimization has been done in order to improve its linearity. The proposed circuit dissipates 6.7 mW and uses in total 672 transistors of PMOS and NMOS types. This ADC is designed and simulated using TSMC’s 0.18 μm CMOS and results show that the proposed circuit works as expected even in presence of process variations.
Cite this paper: M. Njinowa, H. Bui and F. Boyer, "Novel Threshold-Based Standard-Cell Flash ADC," Circuits and Systems, Vol. 3 No. 1, 2012, pp. 29-34. doi: 10.4236/cs.2012.31005.

[1]   S. Y. Sedra and K. C. Smith, “Microelectronic Circuits,” Fourth Edition, Oxford University Press Inc., Oxford, 1998.

[2]   T. Watanabe, T. Mizuno and Y. Makino, “An All-Digital Analog-to-Digital Converter with 12-μV/LSB Using Moving-Average Filtering,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 1, 2003, pp. 120-125. doi:10.1109/JSSC.2002.806263

[3]   D. Lee, et al., “Design Method and Automation of Comparator Generation for Flash A/D Converter,” ACM Portal, No. 5, 2004, pp. 127-155.

[4]   H. Farkhani, M. Meymandi-Nejad and M. Sachdev, “A Fully Digital ADC Using a New Delay Element with Enhanced Linearity,” IEEE International Symposium on Circuits and Systems, ISCAS, 18-21 May 2008, pp. 2406-2409. doi:10.1109/ISCAS.2008.4541940

[5]   M. A. Farahat, F. A. Farg and H. A. Elsimary, “Only Digital Technology Analog-to-Digital Converter Circuit,” International Midwest Symposium on Circuits and Systems, IEEE, Vol. 1, 2003, pp. 178-181.

[6]   B. Yu and W. Black Jr., “A 900 MS/s 6 b Interleaved CMOS Flash ADC,” IEEE Custom Integrated Circuits Conference, Vol. 8, 2001, pp. 149-152.

[7]   G. Geelen, “A 6 b 1.1 GSample/s CMOS A/D Converter,” IEEE International Solid-State Circuits Conference, San Francisco, Vol. 2, 5-7 February 2001, pp. 128- 129. doi:10.1109/ISSCC.2001.912572

[8]   H. Chen, B. Song and K. Bacrania, “A 14-b 20-M Samples/s CMOS Pipelened ADC,” IEEE Journal of Solid-State Circuits, Vol. 6, 2001, pp. 997-1001. doi:10.1109/4.924862

[9]   Y. Park, S. Karthikeyan, F. Tsay and E. Bartolome, “A 10 b 100 M Samples/s CMOS Pipelined ADC with 1.8 V Power Supply,” IEEE International Solid-State Circuits Conference, Vol. 8, 2001, pp. 130-131.

[10]   J. Lin and B. Haroun, “An Embedded 0.8V/480μW 6b/22MHz Flash ADC in 0.13 μm Digital CMOS Process Using Nonlinear Double-Interpolation Technique,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, 2002, pp. 1610-1617. doi:10.1109/JSSC.2002.804333

[11]   F. Munoz, A. P. VegaLeal, R. G. Carvajal, A. Torralba, J. Tombs and J. Ramirez-Angulo, “A 1.1 v Low-Power ΣΔ Modulator for 14-b 16 KHz A/D Conversion,” IEEE International Symposium on Circuits and Systems, Vol. 1, 2001, pp. 619-622.

[12]   B.-S. Song, “Analog Front-End Macro Circuit Design,” International Symposium on VLSI Technology Systems and Applications, Taipei, 8-10 June 1999, pp. 223-226. doi:10.1109/VTSA.1999.786040