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 CS  Vol.12 No.4 , April 2021
Physical Parameter Variation Analysis on the Performance Characteristics of Nano DG-MOSFETs
Abstract: DG-MOSFETs are the most widely explored device architectures for nano-scale CMOS circuit design in sub-50 nm due to the improved subthreshold slope and the reduced leakage power compared to bulk MOSFETs. In thin-film (tsi < 10 nm) DG-MOS structures, charge carriers are affected by tsi- induced quantum confinement along with the confinement caused by a very high electric field at the interface. Therefore, quantum confinement effects on the device characteristics are also quite important and it needs to be incorporated along with short channel effects for nano-scale circuit design. In this paper, we analyzed a DG-MOSFET structure at the 20 nm technology node incorporating quantum confinement effects and various short channel effects. The effect of physical parameter variations on performance characteristics of the device such as threshold voltage, subthreshold slope, ION - IOFF ratio, DIBL, etc. has been investigated and plotted through extensive TCAD simulations. The physical parameters considered in this paper are operating temperature (Top), channel doping concentration (Nc), gate oxide thickness (tox) and Silicon film thickness (tsi). It was observed that quantum confinement of charge carriers significantly affected the performance characteristics (mostly the subthreshold characteristics) of the device and therefore, it cannot be ignored in the subthreshold region-based circuit design like in many previous research works. The ATLASTM device simulator has been used in this paper to perform simulation and parameter extraction. The TCAD analysis presented in the manuscript can be incorporated for device modeling and device matching. It can be used to illustrate exact device behavior and for proper device control.

1. Introduction

The conventional bulk MOSFETs pose scaling limitations beyond 50 nm technology node because of increased Short Channel Effects (SCEs), increased gate- oxide tunneling currents [1] [2] and remarkable mobility degradation [3] [4] [5]. These scaling limits can be overcome by the use of DG-MOSFET structures. Unlike bulk MOSFETs, DG-MOS architectures have two gates which provide an enhanced gate-to-channel coupling capacitance, and therefore, they suffer less from SCEs. The enhanced electrostatic coupling between the gate and the channel allows DG-MOSFETs to be designed with intrinsic channels and hence the problem of mobility degradation and random dopant fluctuations are eliminated in these devices. DG-MOSFETs with ultra-thin (Si) bodies are now being seriously explored for nano-scale CMOS circuit design. In such architectures (with tsi < 10 nm and tox < 3 nm), quantum effects become prominent and they must be taken care of in the analysis and modeling of such devices [6] [7]. As shown in this paper, quantum effects significantly affect device characteristics such as threshold voltage (Vt), transconductance (gm), subthreshold slope (SS), etc. The TCAD analysis can be incorporated for device modeling and device matching. It can be used to illustrate exact device behavior and for proper device control. It can also be used for checking technological parameter fluctuations, reliability evaluation factors, etc.

The results are demonstrated by extensive 2-D TCAD simulation and confirmed analytically at various technology nodes to validate the robustness of the model. Hence, the proffered physical models and the proposed device may be utilized in the progression of reliable and trustworthy TCAD simulation tools for nanodevices. The proposed Nano-DG-MOSFET is the confirmed upcoming device of ultra-low-power VLSI and high-frequency applications. This nano-device can definitely replace the conventional bulk MOSFETs in the future for low power circuits.

2. Methodology

2.1. General Structure

The double gate structure as shown in Figure 1 consists of two gate electrodes: front gate and back gate controlling a conducting channel in between.

2.2. Advantages of DG MOSFET

DG-MOSFETs can easily be scaled down beyond 50 nm technology node due to better immunity to short channel effects. This is because of the enhanced gate to channel coupling capacitance provided by the two gates on either side of the channel. The DG-MOS architectures can be designed with low doped channels which give better carrier mobility and hence, better switching time. The leakage power dissipation caused by off-state currents are minimized in DG-MOSFETs as compared to bulk MOSFETs. The DG-MOSFETs have better current driving

Figure 1. Schematic of a double gate MOSFET.

capability and hence they can be used at much lower threshold and input voltages and consequently power consumption is reduced in DG-MOSFETs. Since no part of the channel is too far away from the two gates, channel current is better controlled by the gate electrodes that gives ideal sub-threshold slope required for sub- threshold region based circuit design [6] [7] [8].

2.3. Quantum Confinement Effect

In order to minimize the drastic increase of short channel effects in highly scaled DG-MOSFETs, very thin oxides and highly doped channels are required which results in very high electric field at the interface. This high electric field leads to the formation of potential well sufficiently steep for inducing quantization of carrier energy levels. The charge carriers then follow the physics of tightly confined particles and they require quantum mechanical treatment. In DG-MOSFETs, carriers are confined due to two main phenomenon: first one is the confinement caused by very high electric field at the interface when oxide thickness is very less (tox < 3 nm) (known as electric field induced quantum confinement and second one is due to the confinement caused by ultra-thin Si film thickness (tsi < 10 nm) (known as tsi induced structural quantum confinement). The effect of these confinements on the device characteristics such as threshold voltage and drain current are quite important. For DG-MOSFETs with Si-film thickness less than 10nm, quantum effects must be incorporated in the analysis and modeling of such device architectures [9] [10] [11].

2.4. Simulation Methodology

The device structure is designed as per the ITRS guidelines and simulated using Silvaco ATLAS Deckbuild editor. Bohm Quantum Potential (BQP) model has been used for incorporating quantum effects; incomplete ionization has been activated in order to account for impurity freeze-out at low temperature. Mobility degradation due to surface roughness scattering and acoustic phonon scattering and concentration dependent mobility is taken care by Lombardi CVT Mobility Model. Shockley-Read-Hall (SRH) model has been used to take recombination effects into account. The impact ionization of carrier under high lateral electric field along with Fermi carrier statistics has also been activated in simulation. The Constant Current Method (CCM) has been used for the threshold voltage extraction

and calculation of DIBL [12] [13] [14]. Vt is extracted from transfer characteristics by measuring the gate voltage at drain current value I D = W L * 10 7 A , where W is channel width and L is channel length. The W L ratio used in the work is 50 [15] [16]. The device parameters selected for simulation are as per the guidelines of International technology roadmap for semiconductors [17] (see Table 1).

3. Simulation Results and Discussion

3.1. Effect of Operating Temperature Variation

Figure 2 represents threshold voltage (Vt) and leakage current (Ioff) variation as a function of channel length for different values of operating temperature (Top). It is evident from the figure that the threshold voltage decreases and leakage current increases with increase in operating temperature at a fixed channel length.

Table 1. Device parameters used for simulation.

Figure 2. Variation of Ioff current (in log scale) and threshold voltage with channel length for different values of operating temperature (Nc = 1015 cm−3, Ns = 1018 cm−3, tox = 2 nm, tsi = 5 nm, ɸG = 4.9 eV).

The threshold voltage (Vt) dependence on temperature is modeled as [18] :

V t T = φ m s T + 2 φ f T + γ 2 φ f 2 + φ f T (1)

where φ m s is metal-substrate contact potential, T is operating temperature, φ f is substrate Fermi potential, γ is body effect coefficient.

As the temperature increases, the first and third term in the equation decreases and second term increases resulting in a net decrease in threshold voltage.

As the threshold voltage decreases with increase in temperature, the leakage current (Ioff) increases as per the following equation [19] :

I o f f = I o e V G S V t n V T [ 1 e V D S V T ] (2)

where I o = W μ o C o x V T 2 e 1.8 L and thermal voltage V T = K T q Cox is gate oxide capacitance, μo is the carrier mobility and n is the subthreshold swing coefficient.

In Figure 3, variation of Ion current and transconductance with channel length for different values of operating temperature is plotted. It can be observed that both the quantities decrease with increasing temperature at a fixed channel length. This is because Ion is proportional to μ(T) and (VGS-Vt(T))2 term and gm is proportional to μ(T) and (VGS-Vt(T)) term. As the temperature increases, (VGS-Vt(T)) term increases because threshold voltage (Vt(T)) decreases as discussed earlier and μ(T) term decreases due to phonon scattering at higher temperature (T > 300 K). The decrease in mobility dominates the term (VGS-Vt(T)) which causes Ion current and transconductance to decrease at higher temperature [20].

Figure 4 shows the variation of subthreshold slope (SS) and Ion-Ioff ratio with channel length for different values of operating temperature. It is clear from the plot that the subthreshold slope and Ion-Ioff ratio degrades with increasing temperature at a fixed channel length. This may be due to the fact that as the temperature increases, Ion current decreases due to mobility reduction caused by phonon scattering and Ioff current increases because of increase in junction leakage current which approximately doubles for every 10˚C rise in temperature.

Figure 5 shows the variation of DIBL with channel length for different values of operating temperature. DIBL increases with increasing temperature at a fixed channel length. This is due to the fact that the threshold voltage degrades when temperature increases.

3.2. Effect of Channel Doping Variation

From Figure 6, the threshold voltage can be found decreasing with increasing channel doping concentration due to the degradation in mobility caused by surface roughness scattering and acoustic phonon scattering. Since, threshold voltage increases with increasing channel doping concentration, the leakage current must reduce according to Equation (2) [21].

Figure 3. Variation of subthreshold slope and Ion - Ioff ratio (in log scale) with channel length for different values of operating temperature (Nc = 1015 cm−3, Ns = 1018 cm−3, tox = 2 nm, tsi = 5 nm, ɸG = 4.9 eV).

Figure 4. Variation of Ion current and transconductance (gm) with channel length for different values of operating temperature (Nc = 1015 cm−3, Ns = 1018 cm−3,tox = 2 nm, tsi = 5 nm, ɸG= 4.9 eV).

Figure 5. Variation of DIBL with channel length for different values of operating temperature (Nc = 1015 cm−3, Ns = 1018 cm−3, tox = 2 nm, tsi = 5 nm, ɸG = 4.9 eV).

Figure 6. Variation of Ioff current (in log scale) and threshold voltage with channel length for different values of channel doping concentration (Ns = 1018 cm−3, tox = 2 nm, tsi= 5 nm, ɸG = 4.9 eV).

In Figure 7, it is observed that Ion current and transconductance decreases with increasing channel doping concentration. This is because of mobility degradation due to columbic scattering and increase in threshold voltage due to increase in Fermi potential of the bulk at high channel doping concentration [22].

Figure 8 represents the variation of Ion-Ioff ratio and subthreshold slope (SS) as a function of channel length for different values of channel doping concentration. It is observed that Ion-Ioff ratio and SS improves at higher channel doping concentration as leakage current (Ioff) is reduced to a great extent [23] [24].

Figure 9 shows that variation of DIBL with channel length for different values of channel doping concentration. It is found that DIBL is lower for higher channel doping concentration at a fixed channel length due to threshold voltage degradation at high doping concentration.

3.3. Effect of Gate Oxide Thickness Variation

In Figure 10, the variation of threshold voltage (Vt) and leakage current (Ioff) at different channel length for different values of oxide thickness is plotted. It is clear from the plot that the threshold voltage increases with decreasing oxide thickness for a fixed channel length. This can be attributed to quantum mechanical effects due to which peak of the inversion layer is found at a finite distance, dm away from the interface resulting in increased effective oxide thickness [25]. The effective increase in oxide thickness is given by Equation (3):

Δ T O X , Q M = ε O X ε S i d m (3)

Also, due to splitting of allowable energy levels into discrete sub-bands with energy levels above that of the classical conduction band edge, energy band gap increases which results in increased effective Fermi potential. This leads to increase in surface potential and thus in increased value for threshold voltage.

Figure 7. Variation of Ion current and transconductance with channel length for different values of channel doping concentration (Ns = 1018 cm−3, tox = 2 nm, tsi = 5 nm, ɸG = 4.9 eV).

Figure 8. Variation of subthreshold slope and Ion/Ioff ratio (in log scale) with channel length for different values of channel doping concentration (Ns = 1018 cm−3, tox = 2 nm, tsi = 5 nm, ɸG = 4.9 eV).

Figure 9. Variation of DIBL with channel length for different values of channel doping concentration (Ns = 1018 cm−3, tox = 2 nm, tsi = 5 nm, ɸG = 4.9 eV).

Figure 10. Variation of Ioff current (in log scale) and threshold voltage with channel length for different values of gate oxide thickness (Nc = 1015 cm−3, Ns = 1018 cm−3, tsi = 5 nm, ɸG = 4.9 eV).

From Figure 11, the leakage current can be observed increasing with increase in oxide thickness as the threshold voltage decreases with increased oxide thickness.

Figure 11 shows the variation of Ion and transconductance with channel length for different values of oxide thickness. It is evident from the plot that both the quantities decrease with increase in oxide thickness at a fixed channel length. This is because of reduced gate to channel coupling capacitance with increase in oxide thickness.

Figure 12 represents the variation of Ion-Ioff ratio and SS with channel length for different values of oxide thickness. As Ion current decreases and Ioff current increases with increase in oxide thickness, Ion-Ioff ratio and SS degrades with increase in oxide thickness.

Figure 13 shows the variation of DIBL with channel length for different values of oxide thickness. It is observed that device with thicker oxide suffers more from DIBL effects. This is due to reduced gate to channel coupling which allows drain to control the channel charges.

3.4. Effect of Silicon Film Thickness Variation

Figure 14 represents the variation of threshold voltage and leakage current with channel length for different Si film thickness values. It is observed from the figure that with decreasing Si film thickness at a fixed channel length, threshold voltage increases. This is because of the fact that the energy quantization increases in channel region with decreasing Si film thickness, tsi.

The leakage current is observed to increase with increase in Si film thickness at a given channel length due to reduced gate to channel coupling capacitance at higher values of Si film thickness.

Figure 15 shows the variation of Ion current and transconductance with channel length for different values of Si film thickness. Ion current decreases with decrease in Si film thickness due to increase in energy quantization in channel region

Figure 11. Variation of Ion current and transconductance with channel length for different values of gate oxide thickness (Nc = 1015 cm−3, Ns = 1018 cm−3, tsi = 5 nm, ɸG = 4.9 eV).

Figure 12. Variation of subthreshold slope and Ion - Ioff ratio (in log scale) with channel length for different values of gate oxide thickness (Nc = 1015 cm−3, Ns = 1018 cm−3, tsi = 5 nm, ɸG = 4.9 eV).

Figure 13. Variation of DIBL with channel length for different values of gate oxide thickness (Nc = 1015 cm−3, Ns = 1018 cm−3, tsi = 5 nm, ɸG = 4.9 eV).

Figure 14. Variation of Ioff current (in log scale) and threshold voltage with channel length for different values of Si film thickness (Nc = 1015 cm−3, Ns = 1018 cm−3, tox = 2 nm, ɸG = 4.9 eV).

Figure 15. Variation of Ion current and transconductance with channel length for different values of Si film thickness (Nc = 1015 cm−3, Ns = 1018 cm−3, tox = 2 nm, ɸG = 4.9 eV).

that leads to enhanced threshold voltage values. The transconductance value is found to decrease with increase in Si film thickness due to reduced gate to chan- nel coupling.

In Figure 16, variation of SS and Ion-Ioff ratio with channel length for different Si film thickness values is shown. The Ion-Ioff ratio is found to decrease with increasing Si film thickness. This is because both Ion and Ioff current increase with increasing Si film thickness but increase in Ioff is more as compared to Ion. Therefore, the ratio Ion-Ioff decreases with increase in Si film thickness. The SS is observed to improve with decreasing Si film thickness as Ion-Ioff ratio is enhanced when Si film thickness is reduced.

Figure 17 shows the variation of DIBL as function of channel length for different values of Si film thickness. It can be observed that the DIBL effect is negligible for longer channel length devices. The DIBL effects are more prominent

Figure 16. Variation of subthreshold slope and Ion - Ioff ratio (in log scale) with channel length for different values of Si film thickness (Nc = 1015 cm−3, Ns = 1018 cm−3, tox = 2 nm, ɸG = 4.9 eV).

Figure 17. Variation of DIBL with channel length for different values of Si film thickness (Nc = 1015 cm−3, Ns = 1018 cm−3, tsi = 5 nm, ɸG = 4.9 eV).

in devices with thicker channel. This is due to weak gate to channel coupling which allow drain to enhance the control over channel charges.

4. Conclusion

The effect of physical parameters variation on performance characteristics of the device such as Vt, SS, ION/IOFF ratio, DIBL, etc. has been studied incorporating quantum confinement effects along with short channel effects. The Vt and Ioff are found to increase and decrease respectively with the increasing channel length, increasing channel doping concentration, decreasing operating temperature, decreasing oxide thickness, decreasing Si film thickness whereas Ion and gm can be seen decreasing with the increasing channel length, increasing temperature, increasing channel doping concentration and increasing gate oxide thickness. Ion and gm increase and decrease respectively with the increase in Si film thickness. The Ion/Ioff ratio and SS can be observed to enhance with the increasing channel length, decreasing operating temperature, and increasing concentration of the channel region, decreasing gate oxide thickness and decreasing Si film thickness. The DIBL effect is more at higher operating temperature, lower channel doping concentration, higher gate oxide thickness and higher Si film thickness. It can be concluded that quantum effects and short channel effects significantly affect the performance characteristics of the device, and therefore, these must be incorporated for nano-scale circuit design. The TCAD analysis can also be used for device modeling and device matching. It can be used to illustrate exact device behavior and for proper device control. It can also be used for checking technological parameter fluctuations, reliability evaluation factors, etc. The results are demonstrated by extensive 2-D TCAD simulation and confirmed analytically at various technology nodes to validate the robustness of the model. Hence, the proffered physical models and the proposed device may be utilized in the progression of reliable and trustworthy TCAD simulation tools for nanodevices. The proposed Nano-DG-MOSFET is the confirmed upcoming device of ultra-low-power VLSI and high-frequency applications. This nano-device can definitely replace the conventional bulk MOSFETs in the future for low power circuits.

Cite this paper: Swami, Y. and Rai, S. (2021) Physical Parameter Variation Analysis on the Performance Characteristics of Nano DG-MOSFETs. Circuits and Systems, 12, 39-53. doi: 10.4236/cs.2021.124004.
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