Physical Parameter Variation Analysis on the Performance Characteristics of Nano DG-MOSFETs

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1. Introduction

The conventional bulk MOSFETs pose scaling limitations beyond 50 nm technology node because of increased Short Channel Effects (SCEs), increased gate- oxide tunneling currents [1] [2] and remarkable mobility degradation [3] [4] [5]. These scaling limits can be overcome by the use of DG-MOSFET structures. Unlike bulk MOSFETs, DG-MOS architectures have two gates which provide an enhanced gate-to-channel coupling capacitance, and therefore, they suffer less from SCEs. The enhanced electrostatic coupling between the gate and the channel allows DG-MOSFETs to be designed with intrinsic channels and hence the problem of mobility degradation and random dopant fluctuations are eliminated in these devices. DG-MOSFETs with ultra-thin (Si) bodies are now being seriously explored for nano-scale CMOS circuit design. In such architectures (with *t _{si}* < 10 nm and

The results are demonstrated by extensive 2-D TCAD simulation and confirmed analytically at various technology nodes to validate the robustness of the model. Hence, the proffered physical models and the proposed device may be utilized in the progression of reliable and trustworthy TCAD simulation tools for nanodevices. The proposed Nano-DG-MOSFET is the confirmed upcoming device of ultra-low-power VLSI and high-frequency applications. This nano-device can definitely replace the conventional bulk MOSFETs in the future for low power circuits.

2. Methodology

2.1. General Structure

The double gate structure as shown in Figure 1 consists of two gate electrodes: front gate and back gate controlling a conducting channel in between.

2.2. Advantages of DG MOSFET

DG-MOSFETs can easily be scaled down beyond 50 nm technology node due to better immunity to short channel effects. This is because of the enhanced gate to channel coupling capacitance provided by the two gates on either side of the channel. The DG-MOS architectures can be designed with low doped channels which give better carrier mobility and hence, better switching time. The leakage power dissipation caused by off-state currents are minimized in DG-MOSFETs as compared to bulk MOSFETs. The DG-MOSFETs have better current driving

Figure 1. Schematic of a double gate MOSFET.

capability and hence they can be used at much lower threshold and input voltages and consequently power consumption is reduced in DG-MOSFETs. Since no part of the channel is too far away from the two gates, channel current is better controlled by the gate electrodes that gives ideal sub-threshold slope required for sub- threshold region based circuit design [6] [7] [8].

2.3. Quantum Confinement Effect

In order to minimize the drastic increase of short channel effects in highly scaled DG-MOSFETs, very thin oxides and highly doped channels are required which results in very high electric field at the interface. This high electric field leads to the formation of potential well sufficiently steep for inducing quantization of carrier energy levels. The charge carriers then follow the physics of tightly confined particles and they require quantum mechanical treatment. In DG-MOSFETs, carriers are confined due to two main phenomenon: first one is the confinement caused by very high electric field at the interface when oxide thickness is very less (*t _{ox}* < 3 nm) (known as electric field induced quantum confinement and second one is due to the confinement caused by ultra-thin Si film thickness (

2.4. Simulation Methodology

The device structure is designed as per the ITRS guidelines and simulated using Silvaco ATLAS Deckbuild editor. Bohm Quantum Potential (*BQP*) model has been used for incorporating quantum effects; incomplete ionization has been activated in order to account for impurity freeze-out at low temperature. Mobility degradation due to surface roughness scattering and acoustic phonon scattering and concentration dependent mobility is taken care by Lombardi CVT Mobility Model. Shockley-Read-Hall (*SRH*) model has been used to take recombination effects into account. The impact ionization of carrier under high lateral electric field along with Fermi carrier statistics has also been activated in simulation. The Constant Current Method (*CCM*) has been used for the threshold voltage extraction

and calculation of *DIBL* [12] [13] [14]. *V _{t}* is extracted from transfer characteristics by measuring the gate voltage at drain current value
${I}_{D}=\frac{W}{L}*{10}^{-7}A$, where

3. Simulation Results and Discussion

3.1. Effect of Operating Temperature Variation

Figure 2 represents threshold voltage (*V _{t}*) and leakage current (

Table 1. Device parameters used for simulation.

Figure 2. Variation of *I _{off}* current (in log scale) and threshold voltage with channel length for different values of operating temperature (

The threshold voltage (*V _{t}*) dependence on temperature is modeled as [18] :

$\frac{\partial {V}_{t}}{\partial T}=\frac{{\phi}_{ms}}{\partial T}+2\frac{\partial {\phi}_{f}}{\partial T}+\frac{\gamma}{\sqrt[2]{2{\phi}_{f}}}+\frac{\partial {\phi}_{f}}{\partial T}$ (1)

where
${\phi}_{ms}$ is metal-substrate contact potential, *T* is operating temperature,
${\phi}_{f}$ is substrate Fermi potential, *γ* is body effect coefficient.

As the temperature increases, the first and third term in the equation decreases and second term increases resulting in a net decrease in threshold voltage.

As the threshold voltage decreases with increase in temperature, the leakage current (*I _{off}*) increases as per the following equation [19] :

${I}_{off}={I}_{o}{\text{e}}^{\frac{{V}_{GS}-{V}_{t}}{n{V}_{T}}}\left[1-{\text{e}}^{\frac{-{V}_{DS}}{{V}_{T}}}\right]$ (2)

where
${I}_{o}=\frac{W{\mu}_{o}{C}_{ox}{V}_{T}{}^{2}{\text{e}}^{1.8}}{L}$ and thermal voltage
${V}_{T}=\frac{KT}{q}$ *C _{ox}* is gate oxide capacitance,

In Figure 3, variation of *I _{on}* current and transconductance with channel length for different values of operating temperature is plotted. It can be observed that both the quantities decrease with increasing temperature at a fixed channel length. This is because

Figure 4 shows the variation of subthreshold slope (*SS*) and *I _{on}*-

Figure 5 shows the variation of *DIBL* with channel length for different values of operating temperature. *DIBL* increases with increasing temperature at a fixed channel length. This is due to the fact that the threshold voltage degrades when temperature increases.

3.2. Effect of Channel Doping Variation

From Figure 6, the threshold voltage can be found decreasing with increasing channel doping concentration due to the degradation in mobility caused by surface roughness scattering and acoustic phonon scattering. Since, threshold voltage increases with increasing channel doping concentration, the leakage current must reduce according to Equation (2) [21].

Figure 3. Variation of subthreshold slope and *I _{on} - I_{off}* ratio (in log scale) with channel length for different values of operating temperature (

Figure 4. Variation of *I _{on}* current and transconductance (

Figure 5. Variation of DIBL with channel length for different values of operating temperature (*N _{c}* = 10

Figure 6. Variation of *I _{off}* current (in log scale) and threshold voltage with channel length for different values of channel doping concentration (

In Figure 7, it is observed that *I _{on}* current and transconductance decreases with increasing channel doping concentration. This is because of mobility degradation due to columbic scattering and increase in threshold voltage due to increase in Fermi potential of the bulk at high channel doping concentration [22].

Figure 8 represents the variation of *I _{on}-I_{off}* ratio and subthreshold slope (

Figure 9 shows that variation of *DIBL* with channel length for different values of channel doping concentration. It is found that *DIBL* is lower for higher channel doping concentration at a fixed channel length due to threshold voltage degradation at high doping concentration.

3.3. Effect of Gate Oxide Thickness Variation

In Figure 10, the variation of threshold voltage (*V _{t}*) and leakage current (

$\Delta {T}_{OX,QM}=\frac{{\epsilon}_{OX}}{{\epsilon}_{Si}}{d}_{m}$ (3)

Also, due to splitting of allowable energy levels into discrete sub-bands with energy levels above that of the classical conduction band edge, energy band gap increases which results in increased effective Fermi potential. This leads to increase in surface potential and thus in increased value for threshold voltage.

Figure 7. Variation of *I _{on}* current and transconductance with channel length for different values of channel doping concentration (

Figure 8. Variation of subthreshold slope and Ion/Ioff ratio (in log scale) with channel length for different values of channel doping concentration (*N _{s}* = 10

Figure 9. Variation of *DIBL* with channel length for different values of channel doping concentration (*N _{s}* = 10

Figure 10. Variation of *I _{off}* current (in log scale) and threshold voltage with channel length for different values of gate oxide thickness (

From Figure 11, the leakage current can be observed increasing with increase in oxide thickness as the threshold voltage decreases with increased oxide thickness.

Figure 11 shows the variation of *I _{on}* and transconductance with channel length for different values of oxide thickness. It is evident from the plot that both the quantities decrease with increase in oxide thickness at a fixed channel length. This is because of reduced gate to channel coupling capacitance with increase in oxide thickness.

Figure 12 represents the variation of *I _{on}*-

Figure 13 shows the variation of *DIBL* with channel length for different values of oxide thickness. It is observed that device with thicker oxide suffers more from *DIBL* effects. This is due to reduced gate to channel coupling which allows drain to control the channel charges.

3.4. Effect of Silicon Film Thickness Variation

Figure 14 represents the variation of threshold voltage and leakage current with channel length for different Si film thickness values. It is observed from the figure that with decreasing Si film thickness at a fixed channel length, threshold voltage increases. This is because of the fact that the energy quantization increases in channel region with decreasing Si film thickness, *t _{si}*

The leakage current is observed to increase with increase in Si film thickness at a given channel length due to reduced gate to channel coupling capacitance at higher values of Si film thickness.

Figure 15 shows the variation of *I _{on}* current and transconductance with channel length for different values of Si film thickness.

Figure 11. Variation of *I _{on}* current and transconductance with channel length for different values of gate oxide thickness (

Figure 12. Variation of subthreshold slope and *I _{on} *-

Figure 13. Variation of DIBL with channel length for different values of gate oxide thickness (*N _{c}* = 10

Figure 14. Variation of *I _{off}* current (in log scale) and threshold voltage with channel length for different values of Si film thickness (

Figure 15. Variation of *I _{on}* current and transconductance with channel length for different values of Si film thickness (

that leads to enhanced threshold voltage values. The transconductance value is found to decrease with increase in Si film thickness due to reduced gate to chan- nel coupling.

In Figure 16, variation of *SS* and *I _{on}-I_{off}* ratio with channel length for different Si film thickness values is shown. The

Figure 17 shows the variation of *DIBL* as function of channel length for different values of Si film thickness. It can be observed that the *DIBL* effect is negligible for longer channel length devices. The *DIBL* effects are more prominent

Figure 16. Variation of subthreshold slope and *I _{on} - I_{off}* ratio (in log scale) with channel length for different values of Si film thickness (

Figure 17. Variation of *DIB*L with channel length for different values of Si film thickness (*N _{c}* = 10

in devices with thicker channel. This is due to weak gate to channel coupling which allow drain to enhance the control over channel charges.

4. Conclusion

The effect of physical parameters variation on performance characteristics of the device such as *V _{t}*,

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