CS  Vol.8 No.5 , May 2017
28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part II
ABSTRACT
This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.
Cite this paper
Mohsen, A. , Harb, A. , Deltimple, N. and Serhane, A. (2017) 28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part II. Circuits and Systems, 8, 111-121. doi: 10.4236/cs.2017.85007.
References
[1]   Collinge, J.P. (1988) Reduction of Kink Effect in Thin-Film SOI MOSFETs. IEEE Electron Device Letters, 9, 97-99.
https://doi.org/10.1109/55.2052

[2]   Federspiel, X., Angot, D., Rafik, M., et al. (2012) 28 nm Node Bulk vs FDSOI Reliability Comparison. 2012 IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, 15-19 April 2012, 3B.1.1-3B.1.4.

[3]   Ramey, S., Ashutosh, A., et al. (2013) Intrinsic Transistor Reliability Improvements from 22 nm Tri-Gate Technology. 2013 IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, 14-18 April 2013, 4C.5.1-4C.5.5.

[4]   Rahman, A., et al. (2013) Reliability Studies of a 22 nm SoC Platform Technology Featuring 3-D Tri-Gate, Optimized for Ultra Low Power, High Performance and High Density Application. 2013 IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, 14-18 April 2013, PI.2.1-PI.2.6.
https://doi.org/10.1109/IRPS.2013.6532105

[5]   Stathis, J. (1999) Percolation Models for Gate Oxide Breakdown. Journal of Applied Physics, 86, 5757-5766.
https://doi.org/10.1063/1.371590

[6]   Planes, N., et al. (2012) 28 nm FDSOI Technology Platform for High-Speed Low-Voltage Digital Applications. 2012 Symposium on VLSI Technology (VLSIT), Honolulu, HI, 12-14 June 2012, 133-134.
https://doi.org/10.1109/VLSIT.2012.6242497

[7]   Auth, C., et al. (2012) A 22 nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors. 2012 Symposium on VLSI Technology (VLSIT), Honolulu, HI, 12-14 June 2012, 131-132.
https://doi.org/10.1109/VLSIT.2012.6242496

[8]   Jan, C.-H., et al. (2012) A 22 nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for Ultra Low Power, High Performance and High Density SoC Applications. 2012 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 10-13 December 2012, 3.1.1-3.1.4.
https://doi.org/10.1109/IEDM.2012.6478969

[9]   Skotnicki, T. (2015) The Success Story of Fdsoi from Equation to Fabrication. Presented at Workshop FDSOI, LETI DAYS, Grenoble, 22 June 2015.

[10]   Hsieh, E.R., Tsai, H.M., et al. (2013) New Observations on the Corner Effect and STI-Induced Effect in Trigate CMOS Devices. 2013 International Conference on Solid State Devices and Materials, 24-27 September 2013.
https://doi.org/10.7567/ssdm.2013.d-2-3

[11]   James, D. (2012) Intel Ivy Bridge Unveiled—The First Commercial Tri-Gate, High-k, Metal-Gate CPU. 2012 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, 9-12 September 2012, 1-4.
https://doi.org/10.1109/CICC.2012.6330644

[12]   Triyoso, D.H., Carter, R., et al. (2015) Factors Impacting Threshold Voltage in Advanced CMOS Integration: Gate Last (FINFET) vs. Gate First (FDSOI). ECS Transactions, MA2015-02, 821.

[13]   Magarshack, P., Flatresse, P. and Cesana, G. (2013) UTBB FD-SOI: A Process/Design Symbiosis for Breakthrough Energy-Efficiency. Design, Automation & Test in Europe Conference & Exhibition, Grenoble, 18-22 March 2013, 952-957.
https://doi.org/10.7873/date.2013.200

[14]   Doris, B., Khakifirooz, A., et al. (2014) Fully Depleted Devices FDSOI and FinFET. In: Brozek, T., Ed., Micro- and Nano-Electronics, CRC Press, Boca Raton, 71-93.

[15]   Bhole, M., Kurude, A. and Pawar, S. (2013) FinFET-Benefits, Drawbacks and Challenges. IJESRT: International Journal of Engineering Sciences & Research Technology, 2.

[16]   Cauchy, X. (Digital Applications Manager, Soitec) and Andrieu, F. (2010) Question and Answers on Fully Depleted SOI Technology. LETI.
www.soitec.com/pdf/SOIconsortium_FDSOI_QA.pdf

[17]   Schaeffer, J. (2015) Extending Moore’s Law with FD-SOI Technology. Global Foundaries Technical Webinar Series.
https://www.chipestimate.com/
https://www.youtube.com/watch?v=7VmQlpXKtHE


[18]   EDPS (2015) Choosing FinFET, FD-SOI, or Bulk Planar FETs (Part 2). Cadence Community.
http://community.cadence.com/cadence_blogs_8/b/ii/archive/2015/05/05
/edps-2015-choosing-finfet-fd-soi-or-bulk-planar-fets-part-2


[19]   Khakifirooz, A., et al. (2010) Fully Depleted Extremely Thin SOI for Mainstream 20 nm Low-Power Technology and Beyond. ISSCC Digest of Technical Papers, 152-153.

[20]   Cathelin, A. (2016) FD-SOI Technology-Analog/RF/MS Focus. STMicroelectronics.
http://cmp.imag.fr/IMG/pdf/28nm_fd-soi_rf_and_analog_03102016.pdf

[21]   Flatresse, P. (2013) UTBB FD-SOI: The Technology for Extreme Power Efficient SOCs. STMicroelectronics.
http://www.cnfm.fr/VersionFrancaise/actualites/Conseil-orientation_2014/
Presentations_CO2014_Web/FDSOI%20Keynote%20-%20CNFM_PFlatresse.pdf


[22]   Ouellette, K. (2015) 28 nm FDSOI Growing Applications and Ecosystem. Presented at Tokyo SOI Meeting, Digital Products Group STMicroelectronics.
http://docplayer.net/35277403-Advances-in-applications-and-ecosystem-
for-fd-soi-technology.html


[23]   Hu, C. (2001) SOI and Nano-Scale MOSFETs. Device Research Conference, Notre Dame, IN, 25-27 June 2001, 3-4.

[24]   Hussain, M.M., et al. (2010) Gate-First Integration of Tunable Work Function Metal Gates of Different Thickness into High-k/Metal Gates CMOS FinFETs for Multi-VTH Engineering. IEEE Transactions on Electron Devices, 57, 626-631.
https://doi.org/10.1109/TED.2009.2039097

[25]   Harris, R., et al. (2007) Critical Components of FinFET Integration: Examining the Density Trade-Off and Process Integration for FinFET Implementation. ECS Transactions, 11, 331-338.
https://doi.org/10.1149/1.2778390

[26]   Fahad, H.M., Hu, C. and Hussain, M.M. (2015) Simulation Study of a 3-D Device Integrating FinFET and UTBFET. IEEE Transactions on Electron Devices, 62, 83-87.
https://doi.org/10.1109/TED.2014.2372695

[27]   Hu, C. and Chen, J. (2012) The 20 nm Moore’s Law Challenge—FinFET versus SOI Technology. Nvidia.
http://electronics.wesrch.com/wequest-EL1UYOB-the-20nm-moore-s-law-
challenge-finfet-versus-soi-technology-with-john-chen-nvidia


 
 
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